UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

16K Session - 10G TCP & UDP Full Offload

  • Part Number: INT- 16K
  • License: SignOnce
  • Vendor: Intilop Inc
  • Program Tier: Member

Product Description

16K Simultaneous TCP/UDP Sessions. 10G TCP Offload Engine + UDP Offload + EMAC+Host_IF - Ultra-Low Latency. Fully Integrated, Verified and System tested TOE, UOE, EMAC & CPU interface. Up to 16K Simultaneous Sessions.


Key Features and Benefits

  • 16K Session TCP&UDP Offload

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-7 Family XC7V450T -3 ISE 14.2 Y 12800 22600 4 0 0 4 157

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 1
Date Current Revision was Released Jul 02, 2014
Release Date of First Version Jul 02, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
High-Level Model Included? Y
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Virtex-7
Software Drivers Provided? Y
Driver OS Support Linux, Win

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST / 14.x
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used VC-707
Industry Standard Compliance Testing Passed Y
Specific Compliance Test TCP Protocol
Test Date Jul 08, 2014
Are Test Results Available? Y
Page Bookmarked