Product Description
The Managed Ethernet Switch (MES) IP is a tri-speed (1GE; 100M; 10M) scalable and highly-optimized Ethernet Switch implementable on AMD FPGA families . The switching structure is based on a full-crossbar non-blocking interconnection matrix between the ports. This approach ensures wire-speed frame processing and very low latency times.
The IP includes optional features like IEEE 1588 Transparent Clock, Jumbo Frames, and VLAN tagging and filtering.
It also supports 2.5/5/10Gbps speed for implementing uplink ports.
Key Features and Benefits
- IEEE 1588v2 Transparent Clock functionalities supported by hardware (P2P-E2E)
- Automatic MAC addresses learning and aging
- Optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
- Very reduced Latency Times thanks to SoCe proprietary MAC address matching mechanism
- Flexible: Fully scalable and configurable: Number of ports, MAC address Table Length, Buffers queue length, IEEE Transparent Clock functionalities
- High Performance Switching: Full-crossbar matrix among ports implemented to allow maximum throughput
- Tri-speed support: Automatic 10/100/1000 speed recognition
- Flexible Management port via AXI4, MDIO, UART or Configuration-over-Ethernet
- VLAN support
- VLAN Priorities support
- 10/100/1000baseTX FX support
- From 3 up to 32 ports
- Protocol based queueing
- RSTP and MRP support
- DLR support: Supervisor node and Beacon based node
- 2.5G/5G/10G support for uplink ports
- Port Mirroring support
- Per port frame rate limiting
- Cut-Through support
- Static Link Aggregation (802.1AX)
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU3CG | -1 | Vivado 2020.1 | Y | 6246 | 16334 | 60 | 0 | 0 | 0 | 125 |
| KINTEX-7 Family | XC7K30T | -1 | Vivado 2020.1 | Y | 6178 | 17211 | 60 | 0 | 0 | 0 | 125 |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2020.1 | Y | 6368 | 17560 | 65 | 0 | 0 | 0 | 125 |
IP Quality Metrics
General Information
| This Data was Current On | Feb 12, 2024 |
| Current IP Revision Number | 21.01 |
| Date Current Revision was Released | May 03, 2021 |
| Release Date of First Version | Oct 07, 2014 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 20 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code, Bitstream |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite, AXI4-Stream |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Xilinx lSim; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | SMARTzynq Brick |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | RFC2544 |
| Test Date | Jan 31, 2020 |
| Are Test Results Available? | Y |