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VESA DSC 1.1 Decoder IP Core

Product Description

Hardent’s DSC v1.1 Decoder IP Core implements video stream decompression functionality compliant with the VESA Display Stream Compression (DSC) v1.1 standard. The DSC algorithms enable visually lossless compression for high-definition applications in the broadcast video, pro A/V, automotive, medical and consumer electronics industries. Applications include video, graphics and display processors, video transport, display monitors, televisions, and DSC standard compliance test and measurement equipment.

The VESA DSC compression standard is compatible with several transport standards including MIPI DSI 1.2, VESA Embedded DisplayPort 1.4a and DisplayPort 1.4. The current release is delivered as a Verilog synthesized gate level netlist supporting a maximum resolution of 1080p60 (FHD).

Additional resolutions such as 4K (4096x2160), 5K (UHD+) and 8K (FUHD), as well as a DSC Encoder IP Core and other target FPGA technologies, are available upon request. Please contact Hardent for further information.

Key Features and Benefits

  • 3:1 and 2:1 compression
  • 8 and 10 bits video components
  • Additional display resolutions available upon request, including 4K (4096x2160), 5K (UHD+) and 8K (FUHD)
  • Current release provides support for a maximum resolution of 1080p60 (FHD)
  • IP provided with comprehensive DSC Decoder wrapper and example integration testbench
  • Input buffering compatible with transport stream over video interfaces
  • Resilient to bitstream corruption
  • Source code verified against the VESA DSC 1.1 C model using a comprehensive test image library
  • Supports all DSC 1.1 mandatory and optional encoding mechanisms
  • YCbCr and RGB 4:4:4 video output format

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K70T -2 Vivado 2015.1 Y 6886 23827 0 1 0 0 65
VIRTEX-7X Family XC7VX330T -2 Vivado 2015.1 N 6886 23827 0 1 0 0 65
Zynq-7000 Family XC7Z015 -2 Vivado 2015.1 N 6886 23827 0 1 0 0 65

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 1.0
Date Current Revision was Released May 22, 2015
Release Date of First Version May 22, 2015

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? Y
Driver OS Support Windows, Linux, OSX


Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST / 2015.1; Synplicity Synplify / Pro-J-2015.03
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor Questa / 10.3; Synopsys VCS / H-2013.06; Cadence NC-Sim / 14.2

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Xilinx Kintex-7 FPGA KC705 Evaluation Kit
Industry Standard Compliance Testing Passed N
Specific Compliance Test N/A
Are Test Results Available? N
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