Product Description
IntelliProp’s IPC-NV163-DT is an industry standard NVMe device interface core that allows companies to build high speed PCIe based storage devices.
Key Features and Benefits
- Compliant to NVMe industry spec
- Compliant for speeds of PCIe Gen1, Gen2 or Gen3
- Application layer interface with processor interface
- Processor interface for register access
- Supports SerDes, PIPE, or SAPIS interface and uses hardblocks when possible
- Synchronous design for easy integration
- Verilog/VHDL support
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU9P | -2 | Vivado ML 2022.2 | Y | 2026 | 7832 | 24 | 5 | 0 | 0 | 100 |
| Zynq-UP-MPSoC Family | XCZU19EG | -2 | Vivado ML 2022.2 | Y | 1818 | 7992 | 24 | 5 | 0 | 0 | 100 |
| Kintex-UP Family | XCKU5P | -2 | Vivado 2020.2 | Y | 1743 | 7684 | 21 | 4 | 0 | 0 | 100 |
| KINTEX-U Family | XCKU040 | -2 | Vivado 2020.2 | Y | 1743 | 7684 | 22 | 0 | 0 | 0 | 100 |
| VIRTEX-U Family | XCVU080 | -2 | Vivado 2020.2 | Y | 1743 | 7684 | 22 | 0 | 0 | 0 | 100 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.82a |
| Date Current Revision was Released | May 05, 2023 |
| Release Date of First Version | Mar 15, 2015 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 18 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Model Formats | Other |
| Integration Testbench Provided | N |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | SDF |
| Commercial Evaluation Board Available? | N |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Instantiation |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Other |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Constrained random testing |
| Assertions | Y |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM / 10.1A |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Kintex Ultrascale |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |