PCI Express DMA Back-End Core (NWL)
Part Number:
DMA Back-End Core
AXI Interface Support:
- AXI4-Stream
- AXI4
- AXI4-Lite
Alliance Program Tier:
Premier
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 LXT
- Virtex-5 FXT
- Virtex-5 LXT
- Spartan-6 LXT
The Northwest Logic DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. Using the core eliminates the need for the user to implement their own DMA design, significantly reducing development time and risk.
Key Features
- Available with either AXI or non-AXI based user interface
- Can be configured with multiple independent DMA Engines
- Companion Windows and Linux DMA Drivers available
- Fully hardware validated
- Provided with a PCI Express Testbench
- Provides high performance, scatter-gather DMA operation
- Provides maximum DMA throughput in both System->Card and Card->System directions
- Supports Packet/Block and Addressed/Non-addressed transfers
- Supports host-based and local descriptors
- Utilization numbers provided in the IP Implementation and Quality Metrics are for a x1 lane PCIe implementation
- Works with Xilinx PCI Express hard cores and Northwest Logic soft PCI Express cores
Target Markets
- Automotive
- Broadcast
- Consumer
- High Performance Computing
- Industrial Scientific Medical
- Wired Communications
- Wireless Communications
- Aerospace & Defense
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2012.1 | Y | 3675 | 9550 | 9 | 0 | 0 | 0 | 250 |
| Zynq-7000 Family | XC7Z045 | -2 | ISE 14.2, ISE 14.2 | Y | 7013 | 14505 | 2 | 0 | 0 | 0 | 250 |
| VIRTEX6LXT Family | XC6VLX240T | -1 | 12.2 | Y | 3471 | 6053 | 5 | 0 | 0 | 0 | 250 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Mar 06,2013 |
| Company Name | Northwest Logic |
| IP Name | PCI Express DMA Back-End Core (NWL) |
| IP Part Number | DMA Back-End Core |
| Current IP Revision Number | 4.13 |
| Date Current Revision was Released | Nov 03,2010 |
| Release Date of first Version | Jul 06,2007 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 190 |
| Can references be made available? | Y |
| Deliverables | |
| IP Formats available for purchase | Netlist; Source Code |
| Source Code Formats(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Virtex-6 |
| Software Drivers Provided? | Y |
| Driver OS Support | Windows, Linux |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | Optimized levels of logic for FPGA operation |
| Synthesis Software Tools Supported / version | Xilinx XST / All; Synplicity Synplify / All; Mentor Precision / All |
| Static Timing Analysis Performed? | Y |
| Standard IP Interface(s) Supported | AXI-4; AXI-Streaming |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Code; Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators supported | Mentor ModelSIM / All; Xilinx lSim / All; Cadence NC-Sim / All; Cadence IUS / All; Mentor Questa / All; Synopsys VCS / All; Other / ALdec RiveraPro/Active-HDL; Other / Synapticad Verilogger |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | Validated on multiple Xilinx Virtex and Spartan platforms |
| Industry standard compliance testing passed | Y |
| Specific compliance test | PCI-SIG Compliance Workshop |
| Test date | 2008-11-18 16:00:00.0 |
| Are test results available? | Y |
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