USB 3.0 Device (USB3_DEV)
- Part Number: USB3_DEV
- Vendor: ASICS World Service, Ltd.
- Partner Tier: Select
Product Description
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface.
Key Features and Benefits
- Bulk, control, interrupt and isochronous endpoints and transfers.
- Compact and cost-effective solution.
- Full duplex operation support.
- Up to 16 fully configurable endpoints.
- Power Management support.
- USB 3.0 PIPE & GTX transceiver interface.
- USB 3.0 SuperSpeed support, 5Gbit/s.
- Integrated DMA engine.
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-7X Family | XC7VX485T | -2 | Vivado 2018.1 | Y | 1632 | 4526 | 12 | 0 | 1 | 1 | 175 |
| KINTEX-7 Family | XC7K325T | -1 | Vivado 2018.1 | Y | 1546 | 4623 | 12 | 0 | 1 | 1 | 170 |
| Zynq-7000 Family | XC7Z045 | -2 | Vivado 2018.1 | Y | 1484 | 4615 | 12 | 0 | 1 | 1 | 175 |
| KINTEX-U Family | XCKU040 | -2 | Vivado ML 2022.1 | Y | 0 | 5768 | 16 | 0 | 0 | 0 | 238 |
| VIRTEX-U Family | XCVU095 | -2 | Vivado 2020.1 | Y | 1473 | 11784 | 12 | 0 | 0 | 0 | 175 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.3 |
| Date Current Revision was Released | Nov 03, 2009 |
| Release Date of First Version | Nov 03, 2009 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 14 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Virtex UltraScale |
| Software Drivers Provided? | Y |
| Driver OS Support | standalone |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference, Instantiation |
| Custom FPGA Optimization Techniques | GTX |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2020.2 |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Cadence NC-Sim / 6.1 |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | HighTech Global Development board |
| Industry Standard Compliance Testing Passed | N |
| Specific Compliance Test | Not Yet |