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DVB-T/H Modulator

  • Part Number: MVD_DVBTH
  • License: SignOnce
  • Vendor: Multi Video Designs
  • Program Tier: Member

Product Description

The DVB-T/H modulator modulates an MPEG-TS DVB-SPI input into a OFDM output in Intermediate Frequency (IF), according to EN 300 744 V1.5.1 standard.

Key Features and Benefits

  • Carrier Suppression > 45dB
  • Configurable Convolutional Rate
  • Configurable in-depth interleaving for DVB-H
  • Configurable support for 2k, 8k and 4k (DVB-H) OFDM modes
  • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • Intermediate frequency output for single DAC (14 bits) or baseband outputs (2 x 16 bits)
  • MER > 42dB
  • MFN or SFN mode
  • Netlist version available for ISE and VIVADO
  • PCR re-stamping (MFN mode)
  • Programmable Guard Interval (1/4, 1/8, 1/16, 1/32)
  • Programmable QPSK, 16-QAM and 64-QAM Symbol Mapping
  • Robust SPI input (discarding incorrect input packets)
  • Single / multi channel
  • Single channel, supports hierarchical transmission
  • Supports variable channel width 5MHz to 8MHz

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2012.1 Y 2738 6272 39 31 1 0 150
Spartan 6T Family XC6SLX45T -3 ISE 13.4 Y 1888 6486 46 29 1 0 150

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 2.2
Date Current Revision was Released Jun 01, 2012
Release Date of First Version Feb 01, 2009

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 9
Can References be Made Available? Y


IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? N/A


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used SP605/ML605/KC705 + Analog Devices AD9739 FMC Card
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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