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Aldec Active-HDL

  • Part Number: AHDL
  • Vendor: Aldec, Inc.
  • Partner Tier: Select
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Product Description

Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution that includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager invokes the AMD ISE or Vivado tool for design synthesis and implementation flows, making it a seamless and flexible design and verification platform. Supports AMD FPGA devices.

Key Features and Benefits

  • Assertion and Coverage based verification: Assertion & Cover viewers waveform /coverage and breakpoint editor. SystemVerilog IEEE 1800 Assertions/Coverage, PSL and Open Vera (OVA).
  • Co-Simualtion: DSP/HDL algorithm MATLAB and Simulink Interfaces.
  • Code Coverage and Linting.
  • Supported Languages: VHDL, Verilog, SystemVerilog IEEE Design/Verification/Assertions, SystemC and EDIF.
  • Design Creation: HDL to text graphics, block and state diagram editing, waveform editing, stimulus generation, language assistant, templates, Code2Graphics converter, Macro/Tcl/Tk and Pearl script support.
  • Pre-Compiled AMD FPGA Libraries.
  • Debugging: Code execution/tracing, waveform compare, memory viewer, coverage, breakpoint editor, Xtrace, Advanced Dataflow, Profiler and SystemC co-debugging .