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CAN 2.0 B Compatible Network Controller (logiCAN)

  • Part Number: logiCAN
  • Vendor: Xylon d.o.o.
  • Program Tier: Premier

Product Description

The logiCAN core provides all features expected from the standard CAN network controller: global masking (acceptance filtering), with separated masks for the Standard and Extended CAN frames, fault confinement, stuff bit generation, CRC and arbitration handling. Like the other Xylon's logicBRICKS IP cores, it is designed and optimized for the Xilinx FPGAs. This core handles messages in a highly automated way that decreases the CPU overhead, which is extremely important for efficient low-cost embedded systems. The core is fully embedded into Xilinx Vivado Design Suite, and its integration with on-chip AXI4-Lite bus is very simple. Parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface.


Key Features and Benefits

  • ARM AMBA AXI4-Lite protocol compliant register interface
  • CAN 2.0B compliant network controller
  • Four programmable acceptance filters for message filtering
  • Supported baud rates up to 1 Mbit per second.
  • Supports standard and extended CAN frames
  • Up to 31 TX and up to 63 RX buffers consuming only one dual-port BRAM

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado 2015.4 Y 216 864 1 0 0 0 100
ARTIX-7 Family XC7A200T -2 Vivado 2015.4 Y 218 873 1 0 0 0 100
Zynq-7000 Family XC7Z045 -2 Vivado 2015.4 Y 229 919 1 0 0 0 100
Spartan 6 Family XC6SLX45 -3 ISE 14.1 Y 311 702 1 0 0 0 176

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 3.2
Date Current Revision was Released Jul 20, 2016
Release Date of First Version Oct 02, 2008

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Model Formats C
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support Bare-metal

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Synthesis Software Tools Supported/Version Xilinx XST / 2016.1
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Assertion
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZC702
Industry Standard Compliance Testing Passed Y
Specific Compliance Test Robert Bosch CAN reference model
Test Date Jun 02, 2015
Are Test Results Available? N
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