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JPEG 2000 multi-channel HD/DCI decoder

  • Part Number: BA109
  • Vendor: Silex Inside SA
  • Program Tier: Certified

Product Description

The BA109 IP core is a JPEG 2000 hardware decoder dedicated to DCI (Digital Cinema Initiatives) and HD video applications. It decodes streams compliant with the ISO/IEC 15444-1 specification (JPEG 2000). It is compliant with the DCI recommendation for video coding. It performs JPEG 2000 decoding on un-tiled large color frames with 4:4:4, 4:2:2 or 4:2:0 sub-sampling.

The core performs the complete video decompression operations of the normalized decoding process: stream parsing and header decoding, entropy decoding, inverse quantization, inverse discrete wavelet transform (IDWT) and inverse color transform (ICT/RCT). It supports a JPEG 2000 j2c file at its input interface and generates decoded samples at its output interface with up to 12 bits per color component.

The core is optimized for speed and is able to deal with the demanding DCI and HD processing requirements: it is able to provide a single-chip FPGA solution for all 2K@24fps, 2K@48fps, 2K3D@24fps, 4K@24fps, 4K3D@24fps, 720p30/60, 1080i and 1080p30/60 distributions.

The flexible FPGA architecture allows the user to build a secure decoder by integrating Barco Silex cryptography decoders.


Key Features and Benefits

  • Compliant with JPEG 2000 (ISO/IEC 15444-1) and DCI (Digital Cinema Initiatives) recommendation.
  • Customizable input bit rate up to 250Mbps / 500Mbps / 1+Gbps / lossless.
  • Full-frame decoding (no tiling).
  • Fully autonomous decoder with automatic parameter extraction, thus requirering minimal user intervention.
  • Fully synchronous design.
  • Multi-channel interface.
  • Pixel depth up to 12 bits per color sample (lossless mode up to 16 bits).
  • Single-chip FPGA solution for single-channel or multi-channel up to 4096x2160 (4K) resolution.
  • XYZ, RGB, YUV (4:4:4 or 4:2:2) color spaces with support for ICT/RCT color transform.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7 Family XC7A200T -1 ISE 14.4 Y 0 0 0 0 0 0 0

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 1.6
Date Current Revision was Released Aug 12, 2010
Release Date of First Version Dec 22, 2006

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Virtex-5
Software Drivers Provided? Y
Driver OS Support Windows XP, Windows Vista, Linux

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Custom FPGA Optimization Techniques Memories & DSP
Synthesis Software Tools Supported/Version Synplicity Synplify / All; Xilinx XST / All
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, executable and documented
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM / All; Other / All

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Virtex-5, Virtex-6
Industry Standard Compliance Testing Passed N/A
Specific Compliance Test N/A
Are Test Results Available? N
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