NANDFLASH-CTRL - NAND Flash memory controller
Part Number:
NANDFLASH-CTRL
AXI Interface Support:
- AXI4
License:
SignOnce
Alliance Program Tier:
Member
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
- IDS Embedded Edition
Device Family Support
- Zynq-7000
- Artix-7
- Virtex-6 LXT
- Virtex-5 LX
- Spartan-6 LX
- Spartan-3E
The NANDFLASH-CTRL IP core is a memory controller that supports both ONFi 3.0 specification and Toggle Mode in NAND Flash devices. The list of supported memory device types inludes high-capacity Triple-Level Cell (TLC), Multi-Level Cell (MLC), Single-Level Cell (SLC) and High-Speed NAND Flash memories. The controller provides System-on-Chip developers with a comprehensive way to minimize time-consuming hardware and software development, as well as leverage embedded application technologies. In the latest release, there has been added support for both ONFi 3.0 and Toggle Mode DDR-2 specifications.
Key Features
- Command queue
- FPGA optimized PHY
- Flexible extremely configurable error correction
- ONFI 3.0 and legacy standard
- Raw NAND, Standard and Enhanced ClearNAND support
- Scatter-gather DMA
- Toggle Mode DDR-2 support
- Various system side interface options (AXI, AHB, PLB, OCP)
Target Markets
- Broadcast
- Consumer
- High Performance Computing
- Aerospace & Defense
- Industrial Scientific Medical
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ARTIX-7 Family | XC7A200T | -3 | ISE 14.1 | N | 3139 | 8626 | 5 | 0 | 0 | 0 | 66 |
| Spartan 6T Family | XC6SLX100T | -4 | ISE 14.1 | Y | 3922 | 8526 | 5 | 0 | 0 | 0 | 66 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Mar 18,2013 |
| Company Name | Evatronix SA |
| IP Name | NANDFLASH-CTRL - NAND Flash memory controller |
| IP Part Number | NANDFLASH-CTRL |
| Current IP Revision Number | 7V01 |
| Date Current Revision was Released | Sep 29,2012 |
| Release Date of first Version | Aug 04,2009 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 4 |
| Can references be made available? | N |
| Deliverables | |
| IP Formats available for purchase | Bitstream; Netlist; Source Code |
| Source Code Formats(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Virtex-6 |
| Software Drivers Provided? | Y |
| Driver OS Support | OS independent drivers |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference; Instantiation; Core Generator |
| Custom FPGA Optimization Techniques | memory buffers, delay lines, clock management |
| Synthesis Software Tools Supported / version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| Standard IP Interface(s) Supported | AXI-4 |
| IP-XACT Metadata Included? | Y |
| Verfification | |
| Is a documented verification plan available? | Executable and documented plan |
| Test Methodology | Constrained random testing |
| Assertions | Y |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators supported | Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | SP605, ML605, ZC702 |
| Industry standard compliance testing passed | N/A |
| Are test results available? | N |
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