Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
AXI Interface Support:
- AXI4-Stream
Bundled With:
ISE
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
- Vivado Design Suite
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Product Details
Documentation
- Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
- Release Notes (PDF)
- Xilinx End User License Agreement
Device Family Support
- Virtex-7 XT
- Virtex-7 HT
Xilinx provides a PCI Express Gen3 integrated block for PCI Express® (PCIe) in the Virtex®-7 XT and HT family of FPGAs. The Virtex-7 FPGA solution for PCI Express Gen3 includes all of the necessary components to create a complete solution for PCIe. Delivered through CORE Generator, the Xilinx for Endpoint and Root Port wrappers simplifies the design process and reduces time-to-market.
This core combined Xilinx Targeted Design Platforms, helps customers develop system solutions.
Key Features
- Compliant with the PCI Express Base Specification 3.0
- Supported Lane width: x1, x2, x4 and x8
- Fully compliant with PCI Express transaction ordering rules
- Optimal buffering for high bandwidth Direct Memory Access (DMA) applications
- Bandwidth scalability interconnect width
- AXI4-Stream Interface
Recommended for:
- High-Performance and High-Bandwidth Applications
- Compute and Data Co-processing Applications
- Medical Imaging, High-Performance Computing & Communications Packet Processing
Deliver:
- The Xilinx Integarated Block for PCIe is provided at no additional cost.