8b/10b Decoder
Bundled With:
ISE
Program:
LogiCORE
Included with Xilinx ISE Software
Product Details
Documentation
Device Family Support
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-3
- Spartan-II
- Spartan-IIE
The 8b/10b Decoder IP core provides the decoding of 10-bit symbols into 8-bit bytes and an accompanying "K" bit. The core also provides the decoding of 268 unique transmitted characters: 256 byte values and 12 special ("K") characters. The core has fully synchronous operation. It tracks "running disparity" to verify that the disparity sequence of the received symbol is valid. The user has the choice of a LUT-based implementation, using FPGA slices, or a block memory-based implementation, using one of the dedicated on-chip block memory blocks. The core has multiple optional inputs and outputs, enabling the user to track data moving through the core. The block RAM implementation can be used to create a secondary ("B") Decoder with almost no additional resource overhead.
For all new designs and designs targeting Virtex®-5, Spartan®-3A and newer families, please use the 8B/10B Decoder Reference Design (XAPP1112) available at the Xilinx.com Documentation Center - under the “Topics” tab.
For all new designs and designs targeting Virtex®-5, Spartan®-3A and newer families, please use the 8B/10B Decoder Reference Design (XAPP1112) available at the Xilinx.com Documentation Center - under the “Topics” tab.