Helion AES Tiny Encryptor/Decryptor
Part Number:
AES_Tiny_Encryptor_Decryptor
Alliance Program Tier:
Premier
Design Tools Support:
- ISE Design Suite
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 HXT
- Virtex-6
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-5
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Spartan-6
- Spartan-6 LX
- Spartan-6 LXT
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Spartan-3E
- Spartan-3
The Helion AES cores implement the FIPS-specified AES algorithm. Two main functions are available, encryption and decryption, and are offered separately for optimum flexibility. The encryptor core accepts a 128-bit plaintext input block, and generates a corresponding 128-bit ciphertext output block using a supplied 128-, 192-, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using a similar AES key as was used for encryption.
Key Features
- Available under the terms of the SignOnce IP License.
- Configurable for full duplex operation or resource shared half duplex operation.
- Designed especially for low data throughput/ultra-low area applications.
- Full dynamic support for all AES key sizes (128, 192 and 256-bits).
- Full support available for all Block Cipher Modes.
- Implements AES (Rijndael) to latest NIST FIPS PUB 197.
Target Markets
- Automotive
- Aerospace & Defense
- Broadcast
- Consumer
- High Performance Computing
- Industrial Scientific Medical
- Wired Communications
- Wireless Communications
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-7 Family | XC7K70T | -1 | ISE 13.2 | Y | 94 | 319 | 0 | 0 | 0 | 0 | 354 |
| SPARTAN3C Family | XC3S200 | -5 | ISE 10.1 | Y | 145 | 266 | 1 | 0 | 0 | 0 | 180 |
| VIRTEX5LX Family | XC5VLX30 | -3 | ISE 10.1 | Y | 78 | 248 | 0 | 0 | 0 | 0 | 389 |
| Spartan 6 Family | XC6SLX45 | -3 | ISE 11.4 | Y | 69 | 232 | 0 | 0 | 0 | 0 | 283 |
| VIRTEX6LXT Family | XC6VLX75T | -3 | ISE 11.2 | N | 71 | 256 | 0 | 0 | 0 | 0 | 488 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Jan 31,2013 |
| Company Name | Helion Technology Limited |
| IP Name | Helion AES Tiny Encryptor/Decryptor |
| IP Part Number | AES_Tiny_Encryptor_Decryptor |
| Current IP Revision Number | nlist_080425 |
| Date Current Revision was Released | Apr 24,2008 |
| Release Date of first Version | Aug 11,2002 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 15 |
| Can references be made available? | Y |
| Deliverables | |
| IP Formats available for purchase | Netlist; Source Code |
| Source Code Formats(s) | VHDL; Verilog |
| High-Level Model Included? | Y |
| High-level Model Format(s) | C |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | N |
| FPGA used on board | N/A |
| Software Drivers Provided? | N/A |
| Driver OS Support | N/A |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference; Instantiation |
| Custom FPGA Optimization Techniques | Hand crafted RPM mactros used in critical datapaths to ensure most optimal timing |
| Synthesis Software Tools Supported / version | Xilinx XST / 11.2 |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | No |
| Test Methodology | Both |
| Assertions | Y |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators supported | Mentor ModelSIM / all |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | Multiple customer platforms |
| Industry standard compliance testing passed | Y |
| Specific compliance test | FIPS AES Validation |
| Test date | 2006-10-04 17:00:00.0 |
| Are test results available? | Y |
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