Aldec Active-HDL

Device Family Support

• Virtex-II
• Virtex-II Pro
• Spartan-3
• Spartan-3 XA
• Spartan-3A
• Spartan-3AN
• Spartan-3DSP
• Spartan-3E
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-6 XA
• Spartan-II
• Virtex-6 SXT
• Spartan-IIE
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-6 -1L
• Virtex-6 CXT
• Virtex-6 HXT
• Virtex-6 LXT

Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution that includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager invokes the Xilinx ISE tool for design, simulation, synthesis and implementation flows, making it a seamless and flexible design and verification platform. Supports Xilinx® FPGA devices.

Key Features

• Assertion and Coverage based verification: Assertion & Cover viewers waveform /coverage and breakpoint editor. SystemVerilog IEEE 1800 Assertions/Coverage, PSL and Open Vera (OVA).
• Co-Simualtion: DSP/HDL algorithm MATLAB and Simulink Interfaces.
• Code Coverage and Linting.
• Debugging: Code execution/tracing, waveform compare, memory viewer, coverage, breakpoint editor, Xtrace, Advanced Dataflow, Profiler and SystemC co-debugging .
• Design Creation: HDL to text graphics, block and state diagram editing, waveform editing, stimulus generation, language assistant, templates, Code2Graphics converter, Macro/Tcl/Tk and Pearl script support.
• Pre-Compiled Xilinx FPGA Libraries.
• Supported Languages: VHDL, Verilog, SystemVerilog IEEE Design/Verification/Assertions, SystemC and EDIF.

Target Markets

• Automotive
• High Performance Computing
• Consumer
• Aerospace & Defense
• Wired Communications
• Wireless Communications