Aldec ALINT

Device Family Support

• Spartan-3
• Spartan-3 XA
• Spartan-3A
• Spartan-3AN
• Spartan-3DSP
• Spartan-3E
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-6 XA
• Spartan-II
• Spartan-IIE
• Virtex-4
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-5
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-6 -1L
• Virtex-6 CXT
• Virtex-6 HXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-II
• Virtex-II Pro

ALINT™ is design analysis tool that identifies critical design issues early in the design stage of ASIC and FPGA designs. The tool points out coding style, functional, and structural problems in Verilog®, VHDL, and mixed-language designs, and prevents them from spreading into the downstream stages of your design flow. Sophisticated static analysis techniques uncover a variety of hidden bugs at the right time when cost and efficiency of modifications are optimal, and highly reduce the risks of redundant design iterations and costly re-spins.

Key Features

• Clock Domain Crossing (CDC) support.
• Configuration Management.
• Cross-Probing of error messages, Violation Viewer.
• Source code checks, design elaboration and synthesis emulation.
• Supports 200 VHDL and Verilog Design Rules.
• User Modified Design Rules.

Target Markets

• Broadcast
• Automotive
• High Performance Computing
• Aerospace & Defense
• Industrial Scientific Medical
• Wired Communications
• Wireless Communications