The Adder/Subtracter IP provides LUT and single Xtreme DSP™ slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable adder/subtracters which operate on signed or unsigned data.
Key Features
- Supports fabric implementation inputs ranging from 1 to 256 bits wide
- Supports Xtreme DSP slice implementation with inputs ranging from 1 to 36 or 48 bits wide (varies with device family selection).
- Optional carry input and output.
- Latency configuration of manual or automatic for maximal speed performance.
- Instantaneous Resource Estimation
- For use with Xilinx CORE Generator™ , Xilinx AccelDSP™ Synthesis Tool, and Xilinx System Generator.