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Block Memory Generator

 

AXI Interface Support:

  • AXI4
  • AXI4-Lite

Bundled With:

Both ISE and Vivado

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

  • ISE Design Suite
  • Vivado Design Suite

The Block Memory Generator is provided under the terms of the XILINX End User License and is included with ISE® and Vivado™ design tools at no additional charge.

Product Details
Documentation
Device Family Support
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6
  • Virtex-5
  • Virtex-4
  • Spartan-3

Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz

The Block Memory Generator LogiCORE™ IP core automates the creation of resource and power optimized block memories for Xilinx FPGAs. Available through the (add ref to Vivado™) ISE® Design Suite CORE Generator™ System, the core enables users to create block memory functions to suit a variety of requirements. Built-in knowledge about Xilinx device architectures allow it to leverage specialized FPGA architectural features to create the most compact, high performance or low power solution.

A Migration Kit is available to automate the migration to latest version of the core.

Key Features

  • Choice of Native Interface, AXI, or AXI4-Lite
  • Example Design helps you get up and running quickly
  • Native interface core
    • Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
    • Performance up to 450 MHz
    • Data widths from 1 to 4096 bits
    • Memory depths from 2 to 128k
    • Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
    • Option to optimize for resource or power
    • Ability to initialize the memories with pre-defined values
    • Supports individual write enable per byte in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6 and Spartan- 3A / XA DSP with or without parity.
    • Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
    • Support for hard and soft Error Correction (ECC) feature
  • AXI interface core
    • Generates Dual Port RAM
    • Performance up to 300 MHz
    • Data widths ranging from 8 to 64 bits
  • Common features in Native interface and AXI cores
    • Variable port aspect rations for dual-port configurations
    • VHDL and Verilog behavioral models optimized for fast simulation times
    • Structural simulation model option for precise simulation
 
 
 
 
 
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