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Block Memory Generator

 

AXI Interface Support:

  • AXI4
  • AXI4-Lite

Bundled With:

ISE

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

  • Vivado Design Suite
  • ISE Design Suite

The Block Memory Generator is provided under the terms of the ISE End User License and is included with ISE software at no additional charge.

Product Details
Documentation
Device Family Support
  • Zynq-7000
  • Artix-7 -2L
  • Artix-7
  • Kintex-7 -2L
  • Kintex-7
  • Virtex-7
  • Virtex-7 -2L
  • Virtex-7 XT
  • Virtex-6 -1L
  • Virtex-6 HXT
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-4 XA
  • Virtex-II Pro
  • Virtex-II
  • Spartan-6 -1L
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3 XA
  • Spartan-3

Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz

The Block Memory Generator LogiCORE™  IP core automates the creation of area and performance optimized block memories for Xilinx FPGAs. Available through the ISE® Design Suite CORE Generator™ System, the core enables users to create block memory functions to suit a variety of requirements. Built-in knowledge about Xilinx device architectures allow it to leverage specialized FPGA architectural features to create the most compact, high performance solution.

A Migration Kit is available to automate the migration of legacy Dual Port Block Memory and Single Port Block Memory LogiCORE IP to the Block Memory Generator style core.

Key Features

  • Choice of AXI, AXI4-Lite or Native interfaces
  • Example Design helps you get up and running quickly
  • Native interface core
    • Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
    • Performance up to 450 MHz
    • Data widths from 1 to 4096 bits
    • Memory depths from 2 to 9M (limited only by memory resources on target device)
    • Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
    • Optimized algorithm for minimum block RAM resource utilization
    • Low Power implementation option to reduce power consumption
    • Configurable memory initialization values
    • Supports individual write enable per byte in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6 and Spartan- 3A / XA DSP with or without parity.
    • Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
    • Leverages built-in Hamming Error Correction capability (ECC) in Virtex-7, Kintex-7, Virtex-6 and Virtex-5 devices for data widths > 64 bits
    • Error injection pins in Virtex-7, Kintex-7, and Virtex-6 allow insertion of single and double-bit errors
    • For data widths < 64 bits, supports soft Hamming Code Error Correction implementation (Virtex-6 and Spartan-6)
  • AXI interface core
    • Generates Dual Port RAM
    • Performance up to 300 MHz
    • Data widths ranging from 8 to 64 bits
  • Common features in Native interface and AXI cores
    • Variable port aspect rations for dual-port configurations
    • VHDL and Verilog behavioral models optimized for fast simulation times
    • Structural simulation model option for precise simulation of memory behaviors
  • Use the “auto-update” feature in CORE Generator to update the core to the latest version in your project.
 
 
 
 
 
 
 
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