Content Addressable Memory (CAM)
Status:
Discontinued
Bundled With:
ISE
Program:
LogiCORE
Product Details
Documentation
Device Family Support
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-3
- Spartan-II
- Spartan-IIE
Product Discontinuation Notice
This IP Core has been discontinued. Effective Date: 03/01/2011
Please note that this core has been discontinued as of March 1, 2011. For new designs requiring CAM functions please use the new Content Addressable Memory reference design and accompanying application note, XAPP1151
The Content Addressable Memory (CAM) IP core can be configured as either an SRL16-based CAM with a 16 clock-cycle write operation and a one clock-cycle search operation, or as a block RAM implementation with only a two clock-cycle write operation. It has full ternary support for both write and search operations. The CAM also supports initialization of binary and ternary CAMs with binary data from a .COE file. The CAM supports optional simultaneous write and search operations, with an output to warn the user of possible collisions. The latest version of the CAM core also supports multiple matches, providing indicators for distinguishing multiple match scenarios, and match resolution logic for generating deterministic results to searches which result in multiple matches.