Cascaded Integrator Comb (CIC) Compiler
AXI Interface Support:
- AXI4-Stream
Bundled With:
ISE
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Included with Xilinx ISE™ Software.
Product Details
Documentation
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-5
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Spartan-3
Requirements
- ISE 13.4 or higher
- ISE IP Update 13.4 or higher
The Cascaded Integrator Comb (CIC) Filter, or Hogenauer filter, is a multiplierless filter architecture that is extremely important for implementing area efficient high sample rate changes in Digital Down Converters (DDC) and Digital Up Converters (DUC). Although its algorithm is quite easily understood, hardware engineers are looking to avoid the time consumed by implementing and maintaining their own IP, while also looking to be able to make quick, informed and resource efficient implementation decisions.
The CIC Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware implementations of their CIC Filter specification. These easily made trade-offs give users the ability to select the most resource and power efficient solutions for their specific applications.
Features in v3.0:
- Supports Virtex®-7, Kintex™-7, Virtex-6 and Spartan®-6 device families
- Supports AXI4-stream interface
- Delivers VHDL demonstration testbench with CORE Generator
Features in v2.0:
- Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device families
Features in v2.0 and v3.0:
- Performance reaching up to 450 MHz for Virtex-6, Virtex-7 and Kintex-7 devices (-1 speed grade)
- Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)
- Support for typical algorithmic requirements: Interpolation and Decimation, three to six CIC stages, one or two differential delays.
- Fixed or programmable rate change from 4 to 8192
- Supports up to 16 channels
- Quick access to the filter frequency response enables algorithmic trade-offs between bit widths, stages, rate change, differential delay, rounding, to be made while also accessing the resource efficiency of the implementation.
- Implementation trade-offs between XtremeDSPTM slice and Logic usage, enable users to achieve the correct balance of resources used and performance.
- Supports input and output streaming interface for multiple channel implementations
- Automatically shares resources when the core is over sampled
- Capability added to specify hardware over sampling specification as a sample period
- Supports automatic CORE Generator™ update
- For use with Xilinx CORE Generator and Xilinx System Generator for DSP™