Included with Xilinx ISE™ Software. Complex Multiplier v5.0 Available Now
The Complex Multiplier IP implements high-performance optimized complex multipliers based on user-specified options. All operands and the results are represented in signed two’s complement format. The operand widths and the result width are parameterizable.
Features in v5.0:
- Supports Virtex®-7, Kintex®-7, Virtex-6 and Spartan®-6 device families
- Support AXI4-stream interface
- Delivers VHDL demonstration testbench with CORE Generator
Features in v3.1
- Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device families
Key Features in v3.1 and v5.0
- Supports inputs ranging from 8 to 63 bits wide
- Supports outputs ranging from 1 to 127 bits wide
- Supports truncation or unbiased rounding.
- Option to use LUTs or embedded multipliers/Xtreme DSP™ slice.
- Optimization for speed or resource utilization is available through implementation using the 3-multiplier or the 4-multiplier solutions
- Instantaneous Resource Estimation of XtremeDSP slice
- For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP