DDS Compiler

Product Details

• Software Requirements
• Ask Xilinx About this Core

Documentation

• DDS Compiler
• Release Notes (PDF)
• Xilinx End User License Agreement

Device Family Support

• Artix-7
• Kintex-7
• Virtex-7
• Virtex-6
• Virtex-5
• Virtex-4
• Spartan-6
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

Requirements

• ISE 13.4 or higher 
• ISE IP Update 13.4 or higher

A critical component in the majority of DSP systems is the sinusoid generator, commonly called a Direct Digital Synthesizer (DDS) or numerically controlled oscillator (NCO). These DDS functions while simple algorithmically presents numerous difficulties to hardware engineers tasked with implementing the function. For example, it is frequently a challenge to limit the memory consumed for high SFDR requirements and also to reach maximum clock performance in the device.

The DDS Compiler eliminates these difficulties and reduces implementation time to the push of a button. Furthermore, the tool provides users with the ability to make implementation trade-offs between XtremeDSP™ slice, Block Memory and Logic in order to achieve the most optimum solution for a given system.

Finally, the DDS Compiler supports all the common algorithmic requirements while achieving maximum Virtex®-6 and Spartan®-6 performance of 450 MHz (-1) and 250 MHz (-2) achievable.

New Features in v5.0

• Option added to configure core as Phase Generator or SIN/COS Lookup Table only.This capability can allow users to custom build a Direct Digital Synthesizer (DDS) to fit individual application needs.
• Increased Spurious Free Dynamic Range (SFDR) from 120dBs to 150dBs.
• Option to configure DDS using system-level parameters (SFDR and Frequency Resolution) or hardware parameters (Phase and Output Width). 
• Option to configure phase increment and phase offset as constant, programmable or dynamic (for modulation).
• SFDR range with no noise shaping increased to 150dBs for low frequency resolution (that is, when Phase Width <= 16-bits. Note that Phase Width was referred to as Accumulator Width in previous versions).
• Taylor Series Corrected can now be used for lower SFDR (that is >66dBs) offering solutions which trade reduced Block RAM resources for increased XtremeDSP slices. (Previously Taylor Series Corrected could only be used for SFDR above 90dBs).
• Phase width has been reduced in multi-channel DDS to give reduced resources while maintaining the same frequency resolution. The update from previous versions automatically increases frequency resolution to maintain the same phase width as previous versions.
• Supports automatic CORE Generator™ update from DDS Compiler v3.0, v2.1 and v2.0.

Key Features

• Performance reaching up to 450 MHz for Virtex-6 devices (-1 speed grade)
• Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)
• Support for the key algorithmic specifications: SFDR, Frequency Resolution, Programmable Phase and Frequency
• Optimal resource implementations
• Implementation trade-offs between Memory types, XtremeDSP slice usage, and Latency vs Performance
• Efficient multi-channel implementations significantly save resources over multiple DDS
• For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP