IEEE 802.16e LDPC Encoder

Product Details

• Ask Xilinx About this Core

Documentation

• IEEE 802.16e LDPC Encoder
• Product Discontinuation Notice (PDF)

Device Family Support

• Virtex-5 LX
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-II Pro
• Virtex-II
• Spartan-3E
• Spartan-3

The IEEE 802e LDPC Encoder Core provides a complete encoding solution for the LDPC encoder as defined in section 8.4.9.2.5 of IEEE P802.16e/D12 "Draft IEEE Standard for local and metropolitan area networks. Part 16:Air interface for fixed and mobile Broadband Wireless Access Systems", 2005-10-14.

A major feature of the core is that it has an extremely low latency. The encoded packet is available at the output, seven clock cycles after the first input bit of the unencoded packet is presented at the input. The output data is then available as a contiguous block.
The LogiCORE™ throughput is dependant on block size and code rate.

Key Features

• Low density parity check encoding for IEEE P802/16e.
• Supports: all block sizes, all code rates.
• Very low latency, seven clock cycles from first data in to first data out).
• Fully optimized for speed and area.
• Any required subset of code rates can be selected at generation to. Enables user to deliver minimal area and maximum performance.
• Fully synchronous design with single clock.
• Readily parameterized through the CORE Generator GUI.