CAN

1. What are the features available in v1.4?

• Spartan™-3AN, Spartan-3A XA, Spartan3A DSP XA, Spartan-3E XA, Virtex™-5 LX , Virtex-5 LXT, Virtex-5 SXT
• Support for ISE® 11.1
• ISO 11898-1, CAN2.0A and CAN2.0B compliant
• Transmit and Receive message FIFOs with a user configurable depth of up to 64 messages
• Parameterized Acceptance Filtering of up to 4 programmable filters
• Maskable error and status interrupts

2. What deliverables are provided with the CAN core?

• Implementation netlist (.NGC)
• Verilog and VHDL functional simulation support (Unisim)
• Example design including both a verilog and VHDL testbench
• Comprehensive set of user documentation
• Datasheet
• Getting Started Users Guide

3. What Xilinx FPGA families and speed grades does the CAN core support?

• Virtex-5 LX 
• Virtex-5 LXT 
• Virtex-5 SXT
• Spartan-3AN
• Spartan-3A XA
• Spartan-3A DSP XA
• Spartan-3E XA

4. Which Xilinx ISE software version supports this latest core?

Please select the System Requirements tab above. 

5. What are the target applications of this core?

Controller Area Network (CAN) is implemented in a large number of industries including automotive, industrial, marine, construction, medical and textile. The CAN core is ideally suited for: 

• Automotive gateways.
• Body control units.
• Automotive test equipment.
• Instrument clusters.
• Sensor controls.
• Industrial networks.

6. What is the availability, cost and licensing terms for the CAN core?

The CAN core is available now. The parameterizable core is configured through a COREGenerator™ software GUI . Purchase of the core entitles you to Xilinx world class technical support and access to any updates which may be provided for a period of one year from your date of purchase. Continued access to updates is available after the first year when you purchase an annual support contract.

The core is provided under the terms of the 

CAN Core License Agreement for XA class devices

CAN Core License Agreement for Non-XA class devices

 For pricing information, 

7. Are there any pinout restrictions for the core?

The pinouts for all configurations of the CAN core are flexible.

8. What are the FPGA resources requirements for the CAN core?

The CAN core's resource requirements are largely dependent of the operating speed and ranges between ~ 450 to 750 slices, depending on the features you select.

The following features can be customized via COREGenerator software to reduce the FPGA resources required:

• TX FIFO Depth choices are: 2, 4, 8, 16, 32, 64
• RX FIFO Depth choices are: 2, 4, 8, 16, 32, 64
• Acceptance Filters choices are: 0, 1, 2, 3, 4

9. How is functional simulation supported?

A gate level Verilog or VHDL Unisim-based functional simulation model tailored to the features selected is created along with the core when you generate the core in the ISE CoreGenerator software.

10. What are the I/O voltage requirements for compatible PHYs?

The core is compatible with 3.3V CAN PHY chips.

11. Has the CAN core been verified in hardware?

Yes. Xilinx has completed hardware testing with 

 CANalyzer and CANstress test equipment using the 

 as the test platform.

The Xilinx CAN core has been validated to be ISO compliant by C&S Group - the worldwide #1 in testing of CAN chip implementations.

12. Is the CAN core available as an EDK core?

Both an XPS CAN and OPB CAN core are fully supported in the Xilinx Embedded Development Kit. XPS CAN should be used in all new designs. A valid LogiCORE IP license for the CAN core is required to use either of these cores.

13. How can I evaluate the core?

There are two levels of evaluation available for the CAN core:

• Simulation-Only
• Full System Hardware Evaluation

To try out the CAN customization GUI and generate a gate level simulation model to functionally evaluate the core in your system ("Simulation-only Evaluation"), follow the instructions.

14. Where can I find a list of known issues?

To find information on the latest known issues and solutions, search on the keywords "CAN Core", on the Technical Answers Search page on support.xilinx.com or click here.