IEEE 802.16e CTC Encoder

Product Details

• Turbo Code Licensing Program
• Ask Xilinx About this Core

Documentation

• IEEE 802.16e CTC Encoder
• Release Notes (PDF)

Device Family Support

• Virtex-5
• Virtex-4
• Spartan-3A DSP
• Spartan-3

The IEEE 802.16e CTC Encoder Core performs duo binary Turbo Encoding of channel data as described in Section 8.4.9 of the IEEE Std 802.16e specification. The coding scheme is a parallel concatenated convolutional code with an input data block of 2N bits. Through parallel processing of the two convolutional encoders, the LogiCORE™ IP is capable of achieving a high throughput encode data rate in excess of 600Mb/s in the slowest speed grade of Virtex™-5 FPGA.

Key Features

• Performs Convolutional Turbo encoding for the mobile WiMAX standard.
• Compliant with IEEE Std 802.16e-2005 and IEEE Std 802.16-2004/Cor1-2005
• Support for all modulation schemes including 64-QAM mode.
• Supports Hybrid ARQ for all block sizes.
• Simultaneous C1 and C2 encoding plus triple buffered memory delivers high throughput encoding rates: 605 Mb/s for block size of 480 bit, 573 Mb/s for 24bit blocks (V5 (-1) device, 303MHz clock)
• Optional Control Signals enable
• Core Generator Module enables easy parameterization