3GPP Downlink Chip Rate

Product Details

• Ask Xilinx About this Core

Documentation

• Product Discontinuation Notice (PDF)
• 3GPP Downlink Chip Rate
• Release Notes (PDF)

Device Family Support

• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Spartan-3A DSP

The 3GPP Downlink Chip Rate LogiCORE™ from Xilinx provides a Release 6 compliant, Xilinx FPGA optimized solution for Femtocell, Picocell and Macrocell solutions. The architecture has been designed to provide efficient use of FPGA logic while also offering a low bandwidth interface to an external DSP or microprocessor to reduce system level overhead using a built in OCP interface. Timing critical operations are performed by the FPGA which also simplifies the software impact with traditional DSP solutions, allowing for an optimum software/hardware balance. The core is fully optimized for speed and area whilst supporting all FDD channels.

Key Features

• Fully scalable solution to support Femtocell through to Macrocell architectures.
• Fully optimized for speed and area.
• Fully synchronous design with independent interface clocks and control interface double buffering.
• Supports HSDPA shared data and control channels (HS-PDSCH and HS-SCCH)
• Support for all FDD channels including scrambling, spreading and weighting; slot formatting; system timing (TCELL, TDPCH, etc); multiple sector support; pilot generation; pilot, TFCI, TPC symbol insertion; STTD encoding and a fully flexible architecture.
• Easily interfaced to external DSP or microprocessor using built-in OCP interfaces.