DVB-S.2 FEC Encoder

Product Details

• Ask Xilinx About this Core

Documentation

• DVB-S.2 FEC Encoder
• Release Notes (PDF)
• Core License Agreement (PDF)

Device Family Support

• Virtex-6 HXT
• Virtex-6 CXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-3A DSP
• Spartan-3

This IP Core has been discontinued as of July 31, 2011 and is no longer orderable.

The DVB-S.2 FEC Encoder core provides a complete Forward Error Correction (FEC) encoding solution for DVB-S.2. This core consists of Outer (BCH), Inner (LDPC) encoding and bit-interleaving stages. The bit interleaver supports the interleaving required by all modulation types, which may be QPSK, 8PSK, 16APSK or 32APSK. All parameters can be changed on a frame-by-frame basis.

Key Features

• Complete Forward Error Correction solution for DVB-S2 (satellite) (ETSI EN 302 307 v1.1.1,2005-03) - BCH Encoder, LDPC (low density parity check) Encoder, Interleaver
• Normal (64k), short frames (16k) and all code rates supported
• Frame length, rates and modulation type can be changed dynamically supporting Adpative Coding Modulation (ACM)
• Serial and parallel  (up to 8 bits) input options giving area versus speed tradeoff
• Foutput options (up to 5 bits) facilitating easier matching with Tx symbol mapper
• Typical max clock for Virtex-5-3 is 243 MHz (4-bit parallel input)
• Throughput of over 900 Mbit/s for normal frame, rate 1/2
• Buffering on input and output, with option for reduced encoding latency
• Full range of handshake signals for easy insertion into baseline DVB-S2.