| 1. What are the new features available in v1.1 Ethernet AVB Endpoint LogiCORE? |
The Ethernet Audio Video Endpoint LogiCORE provides a flexible solution to enhance standard Ethernet MAC functionality. The functionality provides prioritized channels through an existing MAC which are designed to provide a reliable, low latency, Quality of Service for streaming video and audio data. The LogiCORE is designed to emerging P802.1AS and P802.1 Qav standards for the Audio/Video Bridging (AVB) Task Group. It supports AVB Endpoint talker/listener functionality, seamless connection to the Xilinx Tri-Mode Ethernet MAC at speeds of 100 Mb/s and 1 G/s, and driver support for 802.1 AS implementation. |
| 2. What deliverables are provided with the Ethernet AVB Endpoint core? |
The following deliverables are provided with the Ethernet AVB Endpoint core:
Implementation netlist (.NGC)
Driver support for 802.1AS
User-editable top level VHDL and Verilog HDL wrapper
UCF Timing Constraints file
Verilog and VHDL functional simulation support (Unisim)
Sample scripts to run the Xilinx implementation flow and simulation for ModelSIM MTI, Cadence IUS and Synopsis VCS
Example Design, including Demo testbench
Comprehensive set of User Documentation
Datasheet
Getting Started Guide
User Guide
Online Release Notes containing list of New Features and Known Issues.
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| 3. What are the target applications for this product? |
| The Ethernet AVB Endpoint is ideally suited for endpoints in broadcast, profession or consumer audio and video, home networking, and automotive applications. Applications include professional cameras, surveillance cameras, professional mixers, projectors, and automotive head units and networking interface cards. |
| 4. What is the availability, cost and licensing terms for the Ethernet AVB Endpoint core? |
| The Ethernet AVB Endpoint core (DO-DI-AVB-EPT) is available now. Purchase of the core entitles you to Xilinx world class technical support and access to any updates which may be released over a period of one year from your date of purchase. Continued access to updates is available after the first year when you purchase an annual support contract. This core is provided under the terms of the Xilinx LogiCORE Site License Agreement. For pricing information, please contact your distributor or Xilinx FAE. |
| 5. Are there any pinout restrictions for the core? |
| The pinouts for all configurations of the Ethernet AVB Endpoint core are flexible. |
| 6. What are the FPGA resource requirements for the core, and are there any features that can be omitted to reduce this? |
| The Ethernet AVB Endpoint core's resource requirements are largely independent of the operating speed and ranges and are approximately 1463 LUTs and 1826 FFs, and 3 Block Ram depending on the features you select. |
| 7. How is the functional simulation supported? |
| A gate level Verilog or VHDL Unisim-based functional simulation model tailored to the features selected is created along with the core when you generate the core in the ISE CORE Generator. |
| 8. What PHY is the core compatible with? |
| The core has been designed to be compatible with industry standard GE PHYs: see the TEMAC product page http://www.xilinx.com/products/ipcenter/TEMAC.htm for a list of supported interfaces. |
| 9. Has the Ethernet AVB Endpoint core been verified in hardware? |
| The Ethernet AVB Endpoint core has been verified in hardware using both Virtex-5 and Spartan-3A DSP platforms. A test system was created using an embedded Microblaze processor, which had access to all configuration and status registers of the core. The Microblaze also ran the IEEE802.1AS software driver application that is delivered with the core. The Ethernet AVB Endpoint, in both cases, was used with the Xilinx Tri-Mode Ethernet MAC core, using SGMII and GMII/MII interfaces to a standard GE PHY. The Ethernet AVB Endpoint has also been hardware tested with other vendor AVB Endpoint bridge solutions for interoperability. |
| 10. What portions of the Ethernet AVB Specifications does the Ethernet AVB Endpoint core support? |
| The Ethernet AVB supports P802.1AS, and P802.1 Qav. |
| 11. What else do I need to implement a Ethernet AVB Endpoint solution? |
To implement a Ethernet AVB Endpoint, you also need to provide:
Xilinx hard or soft Tri-mode Ethernet LogiCORE
Proprietary customer logic for the Audio/Video and Legacy Ethernet data paths
Connection to an embedded Processor (e.g. Microblaze)
Software based on 802.1 QAT standard (Stream Reservation Protocol) |
| 12. How can I evaluate the core? |
| To try out the Ethernet AVB Endpoint, customize and generate a core using the Customizable GUI from ISE CORE Generator. This will generate a functional Unisim simulation model which you can use to simulate the core in your system ("Simulation-only Evaluation"), follow the instructions regarding Xilinx ISE software requirements, Service Pack levels and IP Update installation requirements described on the Evaluation Options link on the Ethernet AVB Endpoint Product page. |
| 13. Where can I find a list of the known issues? |
| See the IP Release Notes for known issues, new features and patches Answer Browser [back to top] |
