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Ethernet 1000BASE-X PCS/PMA or SGMII

 

Bundled With:

ISE

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

  • Vivado Design Suite
  • ISE Design Suite

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Product Details
Documentation
Device Family Support
  • Artix-7
  • Zynq-7000
  • Kintex-7
  • Virtex-7
  • Virtex-6 -1L
  • Virtex-6 HXT
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-II Pro
  • Virtex-II
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-3A DSP
  • Spartan-3E
  • Spartan-3

Xilinx provides no charge 1000BASE-X PCS/PMA or SGMII standalone LogiCORE™ IP for use in Gigabit Ethernet applications

The Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII IP LogiCORE™ provides an Ethernet Physical Coding Sublayer (PCS) with a choice of either a 1000BASE-X Physical Medium Attachment (PMA) or Serial Gigabit Media Independent Interface(SGMII). 1000BASE-X and SGMII interfaces are implemented using transceivers in Virtex®-7, Kintex™-7, Artix-7, Zynq-7000, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro and Spartan-6 or using Select I/O and the parallel Ten-Bit interface(TBI) interface  in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Spartan®-6, Spartan-3, Spartan-3A / 3AN, Spartan-3A DSP and Spartan-3E families. Xilinx also added support in IDS 12.2 for SGMII over Select I/O for Virtex-6 which integrates XAPP 881, Asynchronous Oversampling over LVDS. On the front end, the IP LogiCORE can also interface seamlessly to an Ethernet MAC through a built-in Gigabit Media Independent Interface (GMII).

Key Features

  • Designed to IEEE 802.3-2008 specification
  • Full-duplex operation
  • Supports speeds up to 1 Gigabit per second
  • Supports Select I/O or Transceiver implementations
  • Optional 1000BASE-X Auto-Negotiation capability for information exchange with a link partner
  • Supports internal or external GMII for interfacing to a MAC or custom logic
  • May be configured and monitored through optional serial MDIO interface
  • Integrates PCS/PMA functions for 1.25 Gbps bandwidth to provide a single-chip solution for 1000BASE-X applications
  • Single chip solution for SGMII function supports 1 Gbps, 100 Mbps, and 10 Mbps Ethernet speeds
  • Delivered through CORE Generator™ technology
  • Implements 8b/10b encoding
  • Supports dynamic switching between SGMII mode and 1000 Base-X PCS/PMA mode
 
Interface
Optional Select I/O or transceiver based implementations:

SGMII over LVDS on Virtex-7 and Kintex-7 using XAPP 523 Asynchronous Oversampling Application Note,
SGMII over LVDS on Virtex-6 using XAPP 881 Asynchronous Oversampling Application Note,
or
A 1000BASE-X PCS with Ten Bit Interface (TBI) to connect to industry standard SerDes devices,
or
An integrated 1000BASE-X PCS/PMA to simplify your board design
A SGMII interface to support multiple data rates
Configure the core with GMII to connect to industry standard MAC devices

Related Information

Related Products

 
 
1.What are the features of this core?
2.What interfaces does the core support?
3.What Xilinx FPGA families and speed grades does the core support?
4.What are the target applications for this product?
5.What is the availability, cost and licensing terms for the core?
6.Are there any pinout restrictions for the core?
7.Are there any features that can be omitted to reduce the resource utilization of the core?
8.Has the core been verified in hardware?
9.Where can I find a list of known issues?
10.What other Ethernet solutions does Xilinx provide?

 1. What are the features of this core?

The Ethernet 1000BASE-X PCS/PMA core is designed to the IEEE 802.3-2008 specification. Features include:

  • Full Duplex operation
  • The core is parameterized through the CORE Generator™, allowing you to tailor the core to your specific feature set requirements
  • Option to implement CRC logic in the Virtex™-II Pro RocketIO™ Multi-Gigabit Transceiver
  • Optional MDIO interface, or simplified interface with configuration vector
 2. What interfaces does the IP core support?
The new core is a parameterized core which may be configured with either of the following interfaces:
  • A 1000BASE-X PCS with a Ten Bit Interface (TBI) for connection to industry standard SerDes devices, or
  • An integrated 1000BASE-X PCS/PMA, which allows you to simplify your board design.
  • SGMII to support multiple data rates

In all of the above cases the front end interface is GMII, which may be either internal to the FPGA, or implemented as an external interface using the FPGA package pins.

 3. What Xilinx FPGA families and speed grades does the core support?
Ten Bit Interface (TBI) Configuration
Integrated 1000BASE-X PCS/PMA or SGMII Configuration
Kintex-7 (-1)
Virtex-7 (-1)
Virtex-6 (-1)
Virtex-5 (-1)
Virtex-4 (-10)
Virtex-II (-4)
Virtex-II Pro (-5)
Spartan-3 (-4)
Spartan-3E (-4)
Spartan-3A (-4)
Spartan-3A / 3AN (-4)
Virtex-II Pro (-5)
Virtex-4 FX (-10)
Virtex-5 LXT (-1)
Spartan-6
 4. What are the target applications for this product?
  • Bridging applications - applications requiring the transfer of Ethernet frames across a medium different from Ethernet, where protocol termination is not required (Examples: GFP-T mapping, switch port interfaces).
  • Porting third party Ethernet MACs to Spartan-6 and Spartan-3 device families, Virtex-6, Virtex-5 LXT, Virtex-4 FX, Virtex-II Pro MGT PCS/PMA.
  • Interfacing Ethernet to other standard interfaces (e.g., SPI-4.2).
  • Backplane applications requiring 1 Gbps data rates
  • Chip-chip or board-board 1 Gbps interfaces
 5. What is the availability, cost, and licensing terms for the core?

This GMII to 1000BASE-X PCS/PMA function was first released as an integrated interface option of the Xilinx Gigabit Ethernet MAC LogiCORE solution (v2.1). It is now available as a standalone core offered at no additional charge to all Xilinx ISE customers. An evaluation version is delivered in standard ISE releases and selected IP Updates for the CORE Generator. This default "simulation-only" evaluation version allows you to integrate the core into your design and perform functional verification and timing analysis. To generate a bitstream for designs containing this core, you must additionally register for this core, request a full access electronic license key, and install the key on your host machine.

Registration and licensing information, as well as instructions for downloading the core can be found in the Register link on the left side at the top of this page.

 6. Are there any pinout restrictions for the core?

The pinouts for all configurations of the core are flexible for the most part.

The main constraints on the PCS/PMA sections of the pinouts are the general guidelines related to the MGTs and DCMs in the Virtex-II Pro™ architecture as described in detail in the RocketIO User Guide.

For the GMII and TBI pinouts, the only constraints are the general guidelines related to I/O Banking in your target FPGA architecture. In addition, it is also recommended that IO's associated with a specific clock domain be grouped together in a separate I/O bank.

 7. Are there any features that can be omitted to reduce the resource utilization of the core?

Yes. The following features may be omitted when customizing the core via the CORE Generator software:

  • Auto-Negotiation per Clause 37 of IEEE 802.3-2008
  • Management interface (MDIO)
  • 1000BASE-X PCS with TBI or PMA
 8. What PHYs are the core compatible with?

Stratos Lightwave RJK-ST11 and R14K-ST11 Optical Transceivers have been tested with the 1000BASE-X PCS/PMA configuration of the Gigabit Ethernet MAC.

The core has been designed to be compatible with industry standard GE PHYs with GMII interfaces and 1000BASE-X compatible optical modules. Please contact your Xilinx FAE for more details on the latest interoperability testing status.

 9. Has the core been verified in hardware?

Xilinx has completed hardware verification of the 1000BASE-X PCS/PMA logic as an integral component of the Gigabit Ethernet MAC core at the University of New Hampshire Interoperability Lab (UNH IOL) using the Xilinx ML320 board as the test platform. Please contact your Xilinx FAE to request a copy of the report.

 10. Where can I find out about known issues?

See the  IP Release Notes for known issues, new features and patches

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 11. What other Ethernet solutions does Xilinx provide?

The core is part of the Xilinx Platform FPGA SystemIO solution, which addresses all aspects of system connectivity in high-performance designs. Xilinx provides the most comprehensive gigabit Ethernet MAC offerings in the programmable industry. In addition to the Ethernet 1000BASE-X PCS/PMA core, Xilinx also provides:

  • a 10/100 Ethernet MAC core with OPB interface for embedded MicroBlaze™ and PowerPC solutions,
  • a 10 Gb Ethernet MAC core
  • a standalone XAUI core
  • Tri-Mode Ethernet MAC core

View a complete listing of Xilinx Ethernet IP solutions for more details.

 
 
 
 
 
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