Interleaver / De-interleaver
Part Number:
EF-DI-INTERLEAV-SITE
AXI Interface Support:
- AXI4-Stream
License:
Core License Agreement
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Included with Xilinx ISE™ Software. Interleaver / De-interleaver v7.0 Available Now
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Product Details
Documentation
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-5
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Spartan-3
Requirements
- ISE 13.4 or higher
- ISE IP Update 13.4 or higher
The Interleaver/De-interleaver LogiCORE™ module is a high-speed, compact design that is fully synchronous, using a single clock. It's parameterizable features support both the Forney Convolutional architecture and the Rectangular Block architecture. The number of branches and branch lengths are parameterizable. The core supports a symbol size from 1 to 256 bits.
Features in v7.0:
- Supports Virtex®-7, Kintex®-7, Virtex-6 and Spartan®-6 device families
- Supports AXI4-stream interface
Features in v6.0:
- Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device families
Features in v6.0 and v7.0:
- Supports many popular standards such as DVB and CDMA2000
- Supports both the Forney Convolutional and the Rectangular Block architectures
- Supports a symbol size from 1 to 256 bits
- Generates example VHDL testbench
- Internal or external symbol RAM
- Convolutional interleaver supports multiple configurations with on-the-fly swapping
- For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP™