64-bit Initiator/Target 133 MHz for PCI-X
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- Virtex-5 FXT
- Virtex-5 LX
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The first complete production release of a PCI-X solution developed by an FPGA provider
The LogiCORE™ IP 64-bit Initiator/Target 133 MHz for PCI-X™ supports the PCI-X v2.0 mode 1 specification and can provide accelerated time-to-market advantage for designers of high 64-bit Initiator/Target for PCI-X designs running at speeds of up to 133 MHz. By using a Xilinx Real PCI-X solution, designers are provided with an alternative to Application Specific Standard Products (ASSPs) and benefit from the flexibility and cost reduction of an FPGA.These new cores create an ideal solution for communication systems and storage area network products such as clustered servers, Ultra 3 SCSI and Fibre Channel based RAID arrays, and multi-port Gigabit devices.The Real PCI-X solution enables customers to design high-performance systems by using Xilinx Smart-IP technology to ensure that the critical minimum, maximum and hold timing required for operation at 133 MHz are satisfied. The solution also verifies the PCI-X v2.0 mode 1 specification through software regression testing using the Xilinx internal test bench that simulates more than six million unique combinations of PCI transactions.
Key Features
- Fully PCI-X 2.0 Mode1 compliant core, 64-bit, 133/66MHz interface with 3.3 V operation
- PCI v3.0-compliant core up to 33MHz
- Customizable, programmable, single-chip solution
- Predefined implementation for predictable timing
- Incorporates Xilinx Smart-IP™ Technology
- 3.3 V PCI-X operation at 33-133 MHz, 3.3 V PCI operation at 0-33 MHz
- Fully verified design tested with Xilinx proprietary testbench
- Optional dual-port FIFOs may be added for maximum burst performance
- Integrated extended capabilities - PCI-X Capability Item, Power Management Capability Item, Message Signalled Interrupt Capability Item
Supported PCI and PCI-X functions
- Full 64-bit Addressing Support
- Up to 6 Base Address Registers
- Expansion ROM Base Address Register
- Cardbus CIS Pointer Register
- Instant-On Base Address Registers
- Memory Write, I/O Read, I/O Write, Configuration Read, Configuration Write, Bus Parking, Special Cycles, Interrupt Acknowledge, Type 0 Configuration Space Header
- Parity Generation, Parity Error Detection, Target Abort, Target Retry, Target Disconnect, Full Command/Status Registers
Supported PCI-X only functions- Split Completion, Split Response
- Memory Read DWORD, Memory Read Block, Memory Write Block
Supported PCI only functions- Memory Read, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI)
Related Information
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