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64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI

 

Part Number:

EF-DI-PCIX64-VE-SITE

License:

Core License Agreement

Program:

LogiCORE

Design Tools Support:

  • ISE Design Suite
  • Vivado Design Suite

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Product Details
Documentation
Device Family Support
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-4 FX
  • Virtex-5 FXT
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-II Pro
  • Virtex-II
  • Virtex-E
  • Virtex
  • Spartan-6
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3E
  • Spartan-3
  • Spartan-II
  • Spartan-IIE

DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI LogiCORE™ IP cores into one convenient product bundle.

The Initiator/Target for PCI ™/PCI-X ™ supports the PCI-X v2.0 mode 1 specification and can provide accelerated time-to-market advantage for designers of high throughput communications systems. Xilinx provides a netlist of the Initiator/Target PCI-X solution for 64-bit designs running at speeds of up to 133 MHz. The 32-bit and 64-bit Initiator/Target for PCI cores enable designers to build a customized PCI solution running at speeds up to 66 MHz.

The DO-DI-PCI-VE product bundle includes the following PCI and PCI-X core configurations

DO-DI-PCI-VE PCI Configurations

FPGA Device

Performance

IP Overviews

Technical Documents

Virtex®-5, Virtex-4, Virtex-II Pro, Spartan®-6 (33 Mhz only), Spartan-3 generation

64-bit
66 MHz

Standalone

Data sheet

Virtex-5, Virtex-4, Virtex-II Pro, Spartan-6 (33 Mhz only), Spartan-3 generation

32-bit
66 MHz

Standalone

Data sheet

Spartan-6 (33 Mhz only), Spartan-3 generation

32-bit
66 MHz

Standalone

Data sheet

Virtex-4, Virtex-II Pro, Spartan-3 generation

32-bit
66 MHz or
33 MHz

OPB/PLB*

Data sheet

Virtex-5, Virtex-4, Spartan-3 generation

32-bit
33 MHz

PLB v4.6*

Data sheet

 DO-DI-PCI-VE PCI-X  Configurations

FPGA Device

Performance

IP

Technical Documents

Virtex-5, Virtex-4, Virtex-II Pro

64-bit
133 MHz

Overview

Data sheet

Please refer to the individual data sheet for each core for part and package support information.

To generate the Core Generator license key for the respective product, please link to the IP Overview page and select access lounge on the left hand side.

Key Features

  • Fully PCI-X 2.0 Mode1 compliant core, 64-bit, 133/66MHz interface with 3.3 V operation
  • Customizable, programmable, single-chip solution
  • Predefined implementation for predictable timing
  • Incorporates Xilinx Smart-IP™ Technology
  • Fully PCI 3.0 core compliant, 64/32-bit, 33 MHz PCI initiator and target interface
  • 3.3v PCI-X operation at 33-133 MHz, 3.3V PCI operation at 0-33 MHz
  • Fully verified design tested with Xilinx proprietary testbench
  • Optional dual-port FIFOs may be added for maximum burst performance
  • Integrated extended capabilities - PCI-X Capability Item, Power Management Capability Item, Message Signalled Interrupt Capability Item
  • Available for configuration and download on the web
 

Supported PCI and PCI-X functions

  • Full 64-bit Addressing Support
  • Up to 6 Base Address Registers
  • Expansion ROM Base Address Register
  • Cardbus CIS Pointer Register
  • Instant-On Base Address Registers
  • Memory Write, I/O Read, I/O Write, Configuration Read, Configuration Write, Bus Parking, Special Cycles, Interrupt Acknowledge, Type 0 Configuration Space Header
  • Parity Generation, Parity Error Detection, Target Abort, Target Retry, Target Disconnect, Full Command/Status Registers

    Supported PCI-X only functions
  • Split Completion, Split Response
  • Memory Read DWORD, Memory Read Block, Memory Write Block

    Supported PCI only functions
  • Memory Read, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI)

Related Information

Related Products

 
 
1.What is PCI-X?
2.What are the applications of PCI-X?
3.What is the difference between PCI and PCI-X?
4.What are the licensing and availability details?
5.How do I get an evaluation copy?
6.What is the PCI technology migration path to support faster design requirements?
7.Which software flows support the PCI-X core?
8.What FPGA families can be targeted using the PCI-X core?
9.Does the PCI-X core support the PCI-X specification?
10.How does the PCI-X core compare with the competitors PCI-X offerings?
             
 1. What is PCI-X?

PCI-X is an extension of the existing PCI bus interface and was pioneered by Compaq, HP, and IBM as a way of increasing the performance of the PCI bus. The initial specification was then turned over to the PCI Special Interest Group (SIG), which has turned it into the PCI-X standard.

The PCI-X spec specifies a bus design that can increases data throughput to a maximum of 1056 Mbytes/sec (over 1 Gbyte/sec). PCI-X is backward compatible with the existing PCI bus at the adapter, device driver, and system level. A PCI-X adapter can operate in a conventional PCI system, and vice-versa.

 2. What are the applications of PCI-X?
Fibre Channel, Gigabit Ethernet and Ultra3 SCSI are the interconnect technologies that require the performance offered by PCI-X. Applications such as Network Interface Cards supporting multiple gigabit devices, Routers, Hubs and Switches, RAID Controllers and Clustered Server Interconnects take advantage of the higher I/O performance that PCI-X offers.
 3. What is the difference between PCI and PCI-X?
Even though PCI-X is an extension of PCI, there are a number of differences that make PCI-X a more efficient implementation:
  • PCI-X doubles the throughput to 1056 Mbytes/sec from 528 Mbytes/sec possible with regular PCI 64/66.
  • PCI-X relaxes the strict timing constraints required by the PCI 64/66 specification, which makes it easier to design.
  • PCI-X improves bus efficiency by enhancing PCI protocol. Enhancements include:
    • Attribute Phase: Uses a 36-bit attribute field that describes bus transactions in more detail than the conventional PCI specification allows. It follows immediately after the address phase and contains several bit assignments that include information about the size of the transaction, ordering of transactions, cache snooping requirements, and the identity of the transaction initiator.
    • Split Transactions: The device requesting the data sends a signal to the target. The target device informs the requester that it has accepted the request. The requester is free to process other information until the target device initiates a new transaction and sends the data to the requester.
    • Optimized Use of Wait States: PCI-X eliminates the use of wait states, except for initial target latency. When a PCI-X device does not have data to transfer, it will remove itself from the bus so that another device can use the bus bandwidth. This provides more efficient use of bus and memory resources.
    • Standard Block Size Movements: With PCI-X, adapters and bridges (host-to-PCI-X and PCI-X to PCI-X) are permitted to disconnect transactions only on naturally aligned 128-byte boundaries. This encourages longer bursts and enables more efficient use of cache-line-based resources such as the processor bus and main memory. It also facilitates a more pipelined architecture within PCI-X devices.
    • Improved Parity Error Handling: Depending upon the ability of the OS Device driver and the OS, the PCI-X devices can recover from a data parity error as opposed to regular PCI.
  • PCI-X supports up to four slots at 66 MHz as opposed to two with PCI 64/66, two slots at 100 MHz and one slot at 133 MHz.
 4. What are the licensing and availability details?
The LogiCORE™ PCI-X 133 MHz core is available today for purchase. Customers who already have purchased the PCI-X core and have a current support contract can download the design files from the product lounge. New customers can register on the PCI-X lounge and access the design files as soon as the registration is approved. The LogiCORE PCI-X interface is provided as a site license and uses the Xilinx PCI products standard licensing agreement.
 5. How do I get an evaluation copy?
The PCI-X evaluation core is available on the PCI/PCI-X evaluation webpage.
 6. What is the PCI technology migration path to support faster design requirements?
The Xilinx PCI-X core is backward and forward compatible. The core offers dual mode capability so from a single bitstream it can dynamically switch between PCI and PCI-X modes at lower speeds. This provides the ability to support legacy designs while moving forward to higher speed technologies. Xilinx is also the first FPGA vendor to provide the PCI Express core. This core is software compatible with PCI-X, again to help support legacy designs while migrating to faster technologies.
 7. Which software flows support the PCI-X core?
The PCI-X core supports Synplicity, Synopsys, and Exemplar flows for Synthesis, ModelTech and Cadence for simulation.
 8. What FPGA families can be targeted using the PCI-X core?
The PCI-X core supports the Virtex-II Pro, Virtex-E and Virtex-II families.
 9. Does the PCI-X core support the PCI-X specification?
The PCI-X core supports Virtex™ Family of devices.

 10. How does the PCI-X core compare with the competitors PCI-X offerings?
The Real-PCI-X™ is the only PCI-X IP that is available and was developed exclusively for an FPGA. Other PLD vendors offer a core that is developed by a third party vendor that supports older PCI-X standards.
 
 
 
 
 
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