DSP48 Macro
Bundled With:
ISE
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Product Details
Documentation
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-5
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Spartan-3
Requirements
- ISE 13.4 or higher
- ISE IP Update 13.4 or higher
The Xilinx LogiCORE™ DSP48 Macro provides an easy-to-use interface that abstracts the XtremeDSP slice and simplifies its dynamic operation by enabling the specification of multiple operations via a set of user defined arithmetic expressions. The specified operations are enumerated and can be selected by the user via a single port on the generated core.
The DSP48 Macro provides a simplified interface to the XtremeDSP slice by the abstraction of all opmode, subtract, alumode and inmode controls to a single SEL port. Further, all CE and RST controls are grouped to a single CE and SCLR port respectively. This abstraction enhances portability of HDL between device families. The DSP48 Macro supports a square latency model where additional register stages are added so all input to output paths have the same latency. The Macro supports 3 latency modes (automatic, tiered and expert). Automatic and tiered are square latency models, the difference being that auto gives fully pipelined whereas tiered allows finer control. This can be useful when utilizing the XtremeDSP slice as a processing engine. Alternatively, all additional pipeline stages can be removed to use the minimum of resources. The DSP48 Macro is recommended for applications that do not require the full versatility of control of the XtremeDSP slices and for applications where portability is a high priority.
Finally, the DSP48 Macro supports all the common instructions of the XtremeDSP slice while achieving maximum Virtex®-7, Kintex®-7, Virtex-6, and Spartan®-6 FPGA performance.
New Features in v2.1
- Support added for Virtex-7 and Kintex-7
- Capability to specify optional separate clock enables and resets for each data and control path registers
Key Features
- Simplified and abstracted interface to XtremeDSP slice enhances ease of use, code readability and portability
- Define XtremeDSP slice operation via a list of user defined arithmetic expressions
- Support for up to 64 instructions
- Supports the XtremeDSP slice pre-adder
- Configurable latency
- Support of signed, two’s complement input data
- For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP