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Divider

 

AXI Interface Support:

  • AXI4-Stream

Bundled With:

ISE

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

  • Vivado Design Suite
  • ISE Design Suite

Included with Xilinx ISE™ Software. Divider v4.0 Available Now

Product Details
Documentation
Device Family Support
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6
  • Virtex-5
  • Virtex-4
  • Spartan-6
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3E
  • Spartan-3
Requirements
  • ISE 13.4 or higher
  • ISE IP Update 13.4 or higher

Traditionally dividers have been avoided by DSP algorithm designers due to the complexity and cost of the hardware implementation. The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division. The integer division can be implemented using Radix-2 non-restoring division, or High-Radix division with prescaling division algorithms.

The Radix-2 algorithm is implemented using the logic fabric and provides up to 32 bits operands along with the ability to control the degree of parallelism used in the algorithm. By controlling the parallelism of the implementation, users can make trade-offs between performance and resources. The High-Radix division with prescaling algorithm is designed to exploit the DSP48 (multiply-add) capability to provide an efficient, low-latency implementation for up to 54 bits operands. The Radix-2 algorithm is suitable for implementing smaller operand division, and High Radix division, better suited for implementing large (above about 25 bits wide) operands.

Features in v4.0:
  • Supports Virtex®-7, Kintex™-7, Virtex-6 and Spartan®-6 device families
  • Supports AXI4-stream interface
  • Delivers VHDL demonstration testbench with CORE Generator
  • Generates an arithmetic division algorithm for integer division with operands of up to 64 bits wide

Features in v3.0:

  • Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device families
  • Generates an arithmetic division algorithm for integer division with operands of up to 54 bits wide

Key Features in v3.0 and v4.0:

  • Performance reaching up to 450 MHz for Virtex-6, Virtex-7 and Kintex-7 devices (-1 speed grade)
  • Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)
  • Performs Radix-2 integer division or High Radix division with prescaling
  • Optional operand widths, synchronous controls, and selectable latency
  • For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP
 
 
 
 
 
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