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10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)

 

Part Number:

EF-DI-10GBASE-KR-PROJ

License:

Core License Agreement

Program:

LogiCORE

Design Tools Support:

  • Vivado Design Suite

Xilinx provides the 10 Gigabit Ethernet PCS/PMA with optional Forward Error Correction (FEC) and auto-negotiation for a backplane (10GBASE-KR) IP core with integrated serial interface to ensure first time success in your design.

Xilinx provides the 10 Gigabit Ethernet PCS/PMA with optional Forward Error Correction (FEC) and auto-negotiation for a backplane (10GBASE-KR) IP core with integrated serial interface to ensure first time success in your design.

The 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) is a Xilinx LogiCORE™ which has an optional FEC (forward error correction) and/or auto-negotiation protocol and link training allowing ultimate flexibility in your solution. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10.3125 Gbps serial single channel PHY over a backplane.
The demand for 10G Ethernet is being driven in the data center as internet data traffic continues to grow. LAN application include Storage Area Networking (SAN), aggregation of 1G Ethernet links, and switch to switch links in the data center, equipment room or in different buildings.

Key Features

  • Designed to 10-Gigabit Ethernet specification IEEE 802.3-2008 clause 49, Forward Error Correction (FEC) clause 74, and Auto-Negotiation clause 73
  • Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802.3-2008 clause 45
  • Available under the Xilinx Project Core License Agreement 
  • Supports LAN mode only 
  • SDR XGMII interface connects seamlessly to the Xilinx 10G Ethernet MAC 
 

 
 
 
 
 
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