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Video Deinterlacer

 

Part Number:

EF-DI-DEINTERLACER-SITE

AXI Interface Support:

  • AXI4-Stream
  • AXI4
  • AXI4-Lite

License:

Core License Agreement

Program:

LogiCORE

Design Tools Support:

  • Vivado Design Suite
  • ISE Design Suite

Get to market quicker using very high quality video processing cores from Xilinx

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Product Details
Documentation
Device Family Support
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6 -1L
  • Virtex-6 HXT
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Spartan-6 -1L
  • Spartan-6 LX
  • Spartan-6 LXT

Xilinx provides a very high quality Video Deinterlacer core to enable faster time-to-market


The Xilinx Video Deinterlacer converts live incoming interlaced video streams into progressive video streams. This process is performed in real time as the input video passes through the Video Deinterlacer. By definition, interlaced images have temporal motion between the two fields that comprise an interlaced frame. The conversion to a progressive format recombines these two fields into one single frame. The raw recombination of interlaced video streams results in unsightly motion artifacts in the progressive output image. For this reason, the Video Deinterlacer uses additional motion tracking and diagonal edge enhancement techniques to ensure that these artifacts are removed where possible. This results in a high-quality progressive output image.

Key Features

  • Supports a wide range of industry standard video encoding and packing methods, including:
    • 8, 10 or 12 bits per pixel
    • YUV or RGB color spaces (static or dynamically configurable)
    • 4:2:0, 4:2:2 or 4:4:4 packing (static or dynamically configurable)
  • Supports highly scalable resolutions from 128x128 up to 2048x2048, such as:
    • Standard SD formats: 480i, 480p, 576i, 576p
    • Standard HD formats: 720p, 1080i, 1080p
    • Digital Cinema 2K
    • All PC resolutions: e.g. 640x480, 1024x768, 1280x1024, 1920x1200
  • Supports progressive pass through, "Progressive Segmented Frames" (PSF) and "Pull down" encoded streams
  • Highly configurable and can be optimized for the smallest FPGA footprint
  • Supports easy integration with other Xilinx Video IP Cores including the OSD, VDMA and Video Scaler
 

1. What deliverables are provided with the Video Deinterlacer core?

The following deliverables are provided with the Video Deinterlacer core:   
Implementation netlist (.NGC)
User-editable top level HDL wrapper
UCF Timing Constraints file
Sample scripts to run the Xilinx implementation flow
Comprehensive set of User Documentation
- Datasheet
- User Guide
- Online Release Notes containing list of New Features and Known Issues

2. What are the target applications for this product?

The Video Deinterlacer core is ideally suited for a wide range of video applications across all industries, such as:
Professional and Broadcast Video
Surveillance
Video Conferencing
Consumer and Automotive Displays
Military Video

3. What is the availability, cost and licensing terms for the Video Deinterlacer core?

The Video Deinterlacer core (EF-DI-Deinterlacer) is available now. Purchase of the core entitles you to Xilinx world class technical support and access to any updates which may be released over a period of one year from your date of purchase. Continued access to updates is available after the first year when you purchase an annual support contract. The Video Deinterlacer core will eventually also be bundled into the Video and Image Processing IP Pack (EF-DI-VID-IMG-IP-PACK). This core is provided under the terms of the Xilinx LogiCORE Site License Agreement. For pricing information, please contact your distributor or Xilinx FAE.

4. Has the Video Deinterlacer core been verified in hardware?

Yes. Xilinx can demonstrate the capabilities of the Video Deinterlacer using the Xilinx ML605 and TED CVK2.0 development platforms
Contact your Xilinx FAE to request a demonstration.

5. What else do I need to implement the Video Deinterlacer?

The Video Deinterlacer is unlikely to be the sole processing block in a video chain, and it is likely that a color space converter, format converter, video interfaces and maybe a scaler will be required. All of these cores are available from Xilinx and a sample Real Time Video Engine reference design is also available to provide a typical use case as well as provide a framework for connecting different video and imaging blocks together.

 
 
 
 
 
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