Digital Pre-Distortion (DPD)


Part Number:


AXI Interface Support:

  • AXI4-Lite
  • AXI4-Stream


Core License Agreement



Design Tools Support:

  • Vivado Design Suite

Xilinx provides a market leading DPD solution for common wireless standards that reduces base station equipment

Digital Pre-Distortion (DPD) is one of the most fundamental building blocks in wireless communication systems today. It is used to increase the efficiency of Power Amplifiers. By reducing the distortion created by running Power Amplifiers in their non-linear regions, Power Amplifiers can be made to be far more efficient. Wireless base stations not employing CFR or DPD algorithms typically exhibit low efficiency, and therefore high operational and capital equipment costs. A typical Class AB LDMOS Power Amplifier with WCDMA waveforms may have approximately 8-15% efficiency. With CFR and DPD turned on, this efficiency can grow to as much as 30-40%, resulting in tremendous savings in CapEx and OpEx for network operators. With later generations of Power Amplifier design leveraging Doherty architectures, efficiencies in the 40%+ range with Xilinx DPD are possible.

The Xilinx DPD core reduces implementation time by providing a high performance DPD solution to customers as a parameterizable core rather than one that needs to be customized by hand. Furthermore, Xilinx DPD is tuned for implementation in Xilinx FPGAs, resulting in a very small FPGA footprint and the lowest cost FPGA solution available today.

Xilinx DPD v7.0 supports the following air interface standards:

  • LTE/LTE-Advanced
  • WiMAX
  • CDMA2000
  • MC-GSM

Xilinx has now released a Vivado Early Access Design version of the DPD v7.0.  The core release of DPD v7.0 is currently planned in Q3 2014 and the date may be subject to change.  Customers interested to evaluate the EA design version must request using

Key Features

FeatureDPD v6.0DPD v6.1DPD v7.0 EA
Typical correction performance25-35dB25-35dB35-40dB
Maximum iBW100MHz100MHz100MHz
Supported Tx Antennas1, 2, 4 or 81, 21, 2
Supported Clocks per output sample (to allow DPD sample rate vs FPGA clock rate trade off)0.5 (supports 600+MSPS DACs), 1, 2, 3, 4 10.5, 1
Feedback path1Fs, 2Fs Real or Complex IF1Fs, 2Fs Real or Complex IF1Fs, 2Fs Real or Complex IF
Support for Export Compliant ADCYesNoYes
Variable memory matrix parameterization to allow narrow band vs broad band area trade offYes, 6Yes, 2Yes, only runtime
Supports processor hardware acceleration to reduce coefficient update timesYes, 3NoYes
Typical update time for 1 antenna, with hardware acceleration<200ms<150ms (with no acceleration)<100ms
Supported DevicesVirtex-6, 7 Series (MicroBlaze)Zynq (ARM)Zynq (ARM)