Digital Pre-Distortion (DPD)

Documentation

• Digital Pre-Distortion (DPD)
• Release Notes (PDF)
• Core License Agreement (PDF)

Device Family Support

• Zynq-7000
• Artix-7
• Kintex-7 -2L
• Kintex-7
• Virtex-7
• Virtex-7 -2L
• Virtex-7 XT
• Virtex-6 CXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Spartan-6 LX
• Spartan-6 LXT

Xilinx provides a market leading DPD solution for common wireless standards that reduces base station equipment

Digital Pre-Distortion (DPD) is the one of the most fundamental building blocks in wireless communication systems today. It is used to increase the efficiency of Power Amplifiers. By reducing the distortion created by running Power Amplifiers in their non-linear regions, Power Amplifiers can be made to be far more efficient. Wireless base stations not employing CFR or DPD algorithms typically exhibit low efficiency, and therefore high operational and capital equipment costs. A typical Class AB LDMOS Power Amplifier with WCDMA waveforms may have approximately 8-15% efficiency. With CFR and DPD turned on, this efficiency can grow to as much as 30-40%, resulting in tremendous savings in CapEx and OpEx for network operators. With later generations of Power Amplifier design leveraging Doherty architectures, efficiencies in the 40%+ range with Xilinx DPD are possible.

The Xilinx DPD core reduces implementation time by providing a high performance DPD solution to customers as a parameterizable core rather than one that needs to be customized by hand. Furthermore, Xilinx DPD is tuned for implementation in Xilinx FPGAs, resulting in a very small FPGA footprint and the lowest cost FPGA solution available today.

• LTE/LTE-Advanced
• TD-SCDMA
• WCDMA
• WiMAX
• CDMA2000

Key Features

• Support for variable clocks per output sample (0.5x(NEW), 1x, 2x, 3x, 4x) to allow DPD sample rate vs area trade off.
  • New 0.5x supports 600+MSPS DAC/ADC on -1 devices
• Support for 1, 2, 4, 8 Transmit Antennas, with a shared update engine.
• Supports 1Fs, 2Fs Real or Complex IF feedback path
  • Support for FIFO ADC interface (burst mode ADC devices. Eg. AD6641)
• Supports variable memory matrix parameterization allowing area vs correction performance trade off
  • 2 additional architecture options for improved correction over wideband (60MHz+) signals
• Supports a range of hardware accelerator options to reduce convergence time
• Support for Transmit Equaliser
  • DPD engine re-used to compute Equaliser tap coefficients.
• Optional Tx and Rx QMC
• Advanced debug interface
• Improved performance for wideband signals (60MHz+), and bursty/HSDPA type waveforms
• ACLR correction up to 33dB
• Support for up to 80MHz of transmit BW