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SPDIF

 

Part Number:

EF-DI-SPDIF-SITE

AXI Interface Support:

  • AXI4-Stream
  • AXI4-Lite

License:

Core License Agreement

Program:

LogiCORE

Design Tools Support:

  • ISE Design Suite
  • Vivado Design Suite

Need Help?

Documentation
Device Family Support
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6
  • Spartan-6 LX
  • Spartan-6 LXT

Xilinx provides a SPDIF Controller to transport audio data.

The Sony/Philips Digital Interconnect Format (SPDIF) core is a digital audio interface controller that implements the International Electronic Commission (IEC) 60958-3 interface for transmitting and receiving audio data. This includes standard bus interfaces to the AMBA® AXI4-Lite and AXI4-Stream interfaces, allowing for integration to the IP core with a master system for further processing of audio data. Data collected by the LogiCORE™ IP SPDIF core is stored in the core’s internal FIFO, allowing the system to process a relatively slow audio stream.

Key Features

  • Configurable as an SPDIF audio data transmitter or an SPDIF audio data receiver
  • Configurable FIFO buffer stores the audio sample data CRC checking or insertion for transmitted frames
  • IEC 60958-3 standard SPDIF digital audio bus interface
  • Audio sample lengths of 16/20/24 bits
  • Variable sampling rates (32 kHz/44.1 kHz/48 kHz/88.2 kHz/96 kHz/176.4 kHz/192 kHz)
  • Based on AXI4-Stream specification
  • Continuous aligned streams only (no null or positional bytes transmission support)
  • Register access support through the AXI4-Lite interface
 

 1. What are the new features in v3.2?
  • ISE 14.2 support
  • Vivado 2012.2 support
 2. What deliverables are provided with the SPDIF core?

The following deliverables are provided with the SPDIF core:

  • Implementation netlist (.NGC)
  • User-editable top level HDL wrapper
  • Demonstration Testbench
  • MTI Simulation Scripts
  • Comprehensive set of User Documentation
  • Product Guide
 3. What Xilinx FGPA families and speed grades does the SPDIF core support?

Please refer to the SPDIF Offerings and System Requirements Schedule for information on supported FPGA device families and speed grades.

 4. What are the target applications for this product?

The SPDIF is ideally suited for providing audio connectivity. It support different sample rate from 44.1 KHz – 192 KHz.

 5. What are the resource requirements for the core, and are there any features that can be omitted to reduce this?

The SPDIF Transmitter core's resource requirement ranges between ~212 to 267 LUTs, ~212 to 287 Flops and 1 BRAM for Spartan-6.

The SPDIF Receiver core's resource requirement ranges between ~372 to 1506 LUTs, ~346 to 1646 Flops and 1 BRAM for Spartan-6.

 6. What else do I need to implement a SPDIF?

To implement a SPDIF, you also need to provide:

Software Driver.
 7. How can I evaluate the core?

'Simulation-Only", and

"Full System Hardware Evaluation".

For more information, refer to the Evaluate link for the SPDIF Core.

 
 
 
 
 
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