FD-based Parallel Register
Bundled With:
ISE
Program:
LogiCORE
Device Family Support
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-3E
- Spartan-3
- Spartan-IIE
The FD-based Parallel Register is a flip-flop-based data register that features 1 to 64 bits width. Options provided are Clock Enable; Asynchronous Set, Clear and Init; and Synchronous Set, Clear and Init. It can optionally generate output as a Relationally Placed Macro (RPM) or as unplaced logic. Output in RPM form is columnar.