Fast Fourier Transform (FFT)

Product Details

• Software Requirements
• Download Bit Accurate C-Model for FFT
• Ask Xilinx About this Core

Documentation

• Fast Fourier Transform
• Release Notes (PDF)
• Xilinx End User License Agreement

Device Family Support

• Kintex-7
• Artix-7
• Virtex-7
• Virtex-6
• Virtex-5
• Virtex-4
• Spartan-6
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

Requirements

• ISE 13.4 or higher
• ISE IP Update 13.4 or higher

The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based Digital MODEMs, to Ultrasound, RADAR and CT Image reconstruction algorithms. Although its algorithm is quite easily understood, the variants of the implementation architectures and specifics are significant and are a large time sink for hardware engineers today.

The FFT LogiCORE™ provides four different architectures along with system level fixed point C-models, and reduces typical implementation time from between 3-6 months to the push of a button. It also provides users with the ability to make all the necessary algorithmic and implementation specific trade-offs demanded by both DSP algorithm and hardware engineers. These easily made trade-offs give users the ability to select the most resource and power efficient solutions for the specific point size and transform time needed for their application.

FFT LogiCORE expands the focus on increased dynamic range by increasing data and phase factor width support up to 34 bits and supporting IEEE single precision floating point data type. The floating point option is implemented by utilizing a higher precision fixed-point FFT internally to achieve similar noise performance to a full floating point implementation, with significantly fewer resources.

Key Features

• Performance reaching up to 450 MHz for Virtex-6 devices (-1 speed grade)
• Performance reaching up to 250 MHz  for Spartan-6 devices (-2 speed grade)
• Transform sizes from 8 to 65536 points with the option to be run-time programmable
• Data and phase factor precision from 8 to 34 bits with support for IEEE single precision floating point
• Four architectural implementation options providing the most area efficient implementation for a given data rate
• A fixed point bit-accurate C-Model to enable system level analysis of Xilinx FFT core.
• Algorithmic trade-offs: bit widths, type of scaling and rounding, enable a resource efficient implementation given the algorithmic constraints
• Implementation trade-offs: Type of memory, and XtremeDSP slice usage, enable users to achieve the correct balance of resources used and performance
• Run-time configurable forward or inverse operation and scaling schedule for scaled fixed point
• Efficient multi-channel implementations significantly save resources over multiple FFT implementations
• Programmable Cyclic Prefix Insertion for OFDM systems to in order to significantly reduce memory and area utilized.
• Instantaneous Latency and Resource Estimation of XtremeDSP slice and BRAM allows rapid comparison between key trade-offs
• Configurable input data timing (No offset or 3-cycle input delay)
• IEEE single precision floating point support
• Option to implement complex multipliers using either LUTs, resource-optimized 3-multiplier XtremeDSP slice structure or performance-optimized 4-multiplier XtremeDSP slice structure
• Leverages the pre-adder in Virtex-6 and Spartan-6 XtremeDSP™ slice for complex multiplier implementation
• Supports automatic CORE Generator™ update from Fast Fourier Transform v5.0, Fast Fourier Transform v6.0 and Fast Fourier Transform v7.0
• For use with Xilinx CORE Generator and Xilinx System Generator for DSP™