Fibre Channel Pt. to Pt. Core

The FC core is ideally suited for providing connectivity in point-to-point and fabric topologies for applications such as

• SAN gateways
• Testers and Logic Analyzers
• Server Clusters
• Network, video, e-mail, printing, and database management applications.
• RAID Servers / Embedded RAID Storage
• Workstations in CAD/CAM and industrial simulation environments.
• High Performance Host Motherboards

The FC core (DO-DI-FC) is available now. Purchase of the core entitles you to Xilinx world class technical support and access to any updates which may be released over a period of one year from your date of purchase. Continued access to updates is available after the first year when you purchase an annual support contract.

This core is provided under the terms of the Xilinx Core Site License Agreement. For pricing information, please contact your distributor or Xilinx FAE.

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The pinouts for all configurations of the FC core are flexible.

When laying out the GTP and MGT transceivers and Clock buffers in your design, the general guidelines documented in the appropriate RocketIO User Guide for your target device should be followed. Placement constraints may also be required for the BUFGMUX(s) in the design. .

Sample placements are provided in the UCF file delivered with the HDL wrapper for the core.

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The FC core's resource requirements are largely independent of the operating speed and ranges between ~950 to 2570 slices for Virtex-II Pro and Virtex-4, and 593 to 1960 Virtex-5 slices, depending on the features you select.

The following features are optional and may be omitted when customizing the Point to Point Fibre Channel core via the CORE Generator™ to reduce the FPGA resources required:

• Management Interface
• Statistics Counters (Management Interface must be selected for Statistics support)
• Credit Management
• Speed Negotiation Block

For more detailed information, please refer to the "Device Utilization" section of the Fibre Channel Point to Point Core datasheet.

It should be possible to share clocks between cores and to replicate any necessary placement and timing constraints to suit your application.

• For Virtex-II Pro implementations, multiple RocketIO transceivers can be clocked from the same (B)REFCLK inputs, although there are restrictions. See the RocketIO Multi-Gigabit Transceiver User Guide (UG024) (PDF) for more information.
• For Virtex-4 implementations, multiple RocketIO transceivers can be supplied from a single GT11CLK_MGT component. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076) (PDF) for more information.
• For Virtex-5 implementations,multiple RocketIO transceivers can be supplied from the same (B)REFCLK inputs, although there are restrictions. See the Virtex-5 RocketIO Multi-Gigabit Transceiver User Guide for more information.

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A gate level Verilog or VHDL Unisim-based functional simulation model tailored to the features selected is created along with the core when you generate the core in the ISE CORE Generator.

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The core has been designed to be compatible with industry standard FC PHYs. Most recently it has been tested extensively with the Finisar FCAL SFP FTRJ-8519-P1BNL.

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Yes. Xilinx has successfully completed hardware conformance testing at the University of New Hampshire Interoperability Lab (UNH IOL) for 1Gbps and 2Gbps operation using the Xilinx ML323 board as the test platform.

Contact your Xilinx FAE to request a copy of the 1G and 2G reports.

The FC core supports FC-0, FC-1 and the folllowing functions of FC-2:

• FC_Port state machine (PSM)
• Simple Buffer-to-Buffer Credit Management and Receiver_Ready (R_RDY) responses.

To implement a Fibre Channel Port, you also need to provide:

• An SFP module to connect the differential I/O to optics
• Optical module
• Backend processor interface
• Processor (e.g, Virtex-4 FX or Virtex-5 LXT PowerPC)
• Software

You can Auto-Negotiate between 1Gbps and 2Gbps, or between 2Gbps and 4Gbps.

The FC Logicore IP is "Auto-Negotiation"-ready. To implement Auto-Negotiation support, specify the "Multi-speed" operation. In addition, you will need to either select the hardware speed negotiation option when generating the core to generate the hardware-based speed negotiation block, implement your own speed negotiation logic in the FPGA fabric, or add a processor and your own user software if you wish to save FPGA resources.

No buffers are included with the core. You can easily create your own FIFO buffers using the Xilinx "FIFO Generator" IP core. This core is included with the Xilinx CORE Generator, which is a standard component of the Xilinx ISE software.

There are two levels of evaluation available for the Fibre Channel Core:

• 'Simulation-Only", and
• "Full System Hardware Evaluation".

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• Please refer to the IP Release Notes for known issues, new features and patches