FIFO Generator

Product Details

• FIFO Generator Migration Instructions
• System Requirements
• Ask Xilinx About this Core

Documentation

• FIFO Generator
• Release Notes (PDF)
• Xilinx End User License Agreement

Device Family Support

• Zynq-7000
• Artix-7 -2L
• Artix-7
• Kintex-7 -2L
• Kintex-7
• Virtex-7
• Virtex-7 -2G
• Virtex-7 HT
• Virtex-7 -2L
• Virtex-7 XT
• Virtex-6 -1L
• Virtex-6 HXT
• Virtex-6 CXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-4 XA
• Virtex-II Pro
• Virtex-II
• Virtex-E
• Virtex
• Spartan-6 -1L
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-3A
• Spartan-3A DSP
• Spartan-3AN
• Spartan-3E
• Spartan-3 XA
• Spartan-3
• Spartan-II
• Spartan-IIE

Virtex-7 HT device support in the 14.1 release is Limited Access. Please review the ISE Design Suite v14.1 Release Notes Guide for more information.

The LogiCORE™ IP FIFO Generator core generates fully verified first-in, first-out (FIFO) memory queues ideal for applications requiring in-order data storage and retrieval.

The parameterized core is optimized to deliver maximum performance (up to 500 MHz) with minimal resource utilization. User-customizable settings for width, depth, status flags, memory type, and write/read port aspect ratios, as well as optional support for First Word Fall Through (FWFT) provide ample flexibility to support a wide range of design requirements.

Starting in ISE Design Suite release12.3, the following AXI4 interface options are also supported: AXI4 (memory mapped), AXI4-Stream and AXI4-Lite.

A Migration Guide is available to provide guidance on how to migrate existing designs containing legacy Synchronous FIFO v5.x and Asynchronous FIFO v6.x LogiCORE IP cores to this newer FIFO Generator style core. 

Key Features

• FIFO depths up to 4,194,304 words
• FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations 
• Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
• Independent or common clock domains
• Selectable memory type (block RAM, distributed RAM, shift register, or built-in FIFO)
• Native or AXI interface (AXI4, AXI4-Lite, or AXI4-Stream)
• Optional Packet FIFO configuration helps avoid source end stalling of the AXI data channel for applications which use packet-based data transfer
• Synchronous or asynchronous reset option
• Hamming Error Injection and Correction Checking (ECC) for built-in and block RAM-based FIFOs 
• First-Word Fall-Through (FWFT) 
• Full and Empty status flags, and Almost Full and Almost Empty flags for indicating one-word-left
• Programmable full and empty status flags, set by user-defined constant(s) or dedicated input port(s)
• Configurable handshake signals
• Embedded register option for block RAM and built-in FIFO
• Example Design helps you get up and running quickly
• Fully configurable using the customization GUI in the Vivado™ Design Suite or ISE CORE Generator.
• Use the auto-update feature to convert older versions of the FIFO Memory Generator cores in your design to the latest version (non-AXI to non-AXI)