Main
Home  :  Products  :  Intellectual Property  :  FIFO Generator

FIFO Generator

 

AXI Interface Support:

  • AXI4-Stream
  • AXI4
  • AXI4-Lite

Bundled With:

Both ISE and Vivado

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

  • ISE Design Suite
  • Vivado Design Suite

The FIFO Generator is provided under the terms of the Xilinx End User License and is included with ISE® and Vivado™ design tools at no additional charge.

Product Details
Documentation
Device Family Support
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6
  • Virtex-5
  • Virtex-4
  • Spartan-6
  • Spartan-3
  • Zynq-7000

The LogiCORE™ IP FIFO Generator core generates fully verified first-in, first-out (FIFO) memory queues ideal for applications requiring in-order data storage and retrieval.

The parameterized core is optimized to deliver maximum performance (up to 500 MHz) with minimal resource utilization. Flexible feature set allows users to customize for Memory type, Data width, FIFO depth, Flags, Aspect ratios and First Word Fall Through (FWFT) features.

Starting in ISE Design Suite release12.3, the following AXI4 interface options are also supported: AXI4 (memory mapped), AXI4-Stream and AXI4-Lite.

A Migration Guide is available to provide guidance on how to migrate existing designs to latest version of the core. 

Key Features

  • FIFO depths up to 4,194,304 words
  • FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
  • Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
  • Supports Independent or common clock domains
  • Selectable memory type (Block RAM, Distributed RAM, Shift Register, or Built-in FIFO)
  • Native or AXI interface (AXI4, AXI4-Lite, or AXI4-Stream)
  • Synchronous or asynchronous reset option
  • Supports Packet Mode
  • Supports Error Correction (ECC) and Injection feature for certain configurations
  • Supports First-Word Fall-Through (FWFT)
  • Supports Embedded Register option for Block RAM and Built-in FIFO primitive based implementations
  • Supports – Empty/Full, Almost Empty/Full, and Programmable Empty/Full signals
 
 
 
 
 
/csi/footer.htm