FSL_V20
Bundled With:
EDK
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
Documentation
Device Family Support
- Virtex-6
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
- Virtex
- Spartan-6
- Spartan-3A
- Spartan-3
- Spartan-II
- Spartan-IIE
Fast Simplex Link (FSL) is a uni-directional point-to-point communication channel bus used to perform fast communication between any two design elements on the FPGA when implementing an interface to the FSL bus. Up to 8 master and slave FSL interfaces are available on the Xilinx MicroBlaze™ soft processor. The interfaces are used to transfer data in 2 clock cycles to and from the register file on the processor to hardware running on the FPGA.
Key Features
- Implements a uni-directional point to point FIFO-based communication
- Provide mechanism for unshared and non-arbitrated communication mechanism. This can be used for fast transfer of data words between master and slave implementing the FSL interface.
- Provides an extra control bit for annotating data being transmitted. This control bit can be used by the slaveside interface for multiple purposes. For example, decode the word being transmitted as a control word or use the bit to indicate the start or end of the transmission of a frame.
- FIFO depths can be as low as 1 and as high as 8K.
- Supports both synchronous and asynchronous FIFO modes. This allows the master and slave side of the FSL to clock at different rates.
- Support for SRL16 and dual port LUT RAM or Block RAM based FIFO implementation.