GigEVCore1.0
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The machine vision GigE solution consists of one or more FPGA IP cores to design GigE Vision compliant devices mainly for machine vision market. Devices could be cameras, but also receiving component like specialized GigE frame grabbers. The solution maps GigE Visions’s control channel and message channels to a software implemented part, running on an embedded processor like MicroBlaze. The time critical stream channel is fully implemented in hardware to achieve maximum of throughput. Customer is able to use this core to bring GigE Vision functionality to his device. Software can be customized to support device dependent features. Reference Designs (hardware plus FPGA design) for sending and receiving applications show usage of the core and help implementation on own hardware.
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Spartan-3E | XC3S1200E | -4 | ISE 9.1 | 6870 | 9692 | 17 | 5 | 3 | 0 | 84 |
| General Information | |
| This Data was Current On | Apr 20,2012 |
| Company Name | Sensor to Image GmbH |
| IP Name | GigE for Machine Vision (GigEVCore1.0) |
| IP Part Number | GigEVCore1.0 |
| Current IP Revision Number | 1.2 |
| Date Current Revision was Released | Jun 01,2010 |
| Release Date of first Version | May 01,2009 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 15 |
| Can references be made available? | Yes |
| Deliverables | |
| IP Formats available for purchase | Netlist |
| Source Code Formats(s) | VHDL; C for µBlaze |
| High-Level Model Included? | No |
| High-level Model Format(s) | None |
| Integration Testbench Provided | No |
| Code Coverage Report Provided? | No |
| Functional Coverage Report Provided? | No |
| UCFs Provided? | Yes |
| Commercial Evaluation Board Available? | Yes |
| FPGA used on board | Spartan-6 |
| Software Drivers Provided? | Yes |
| Driver OS Support | Windows and LINUX |
| Implementation | |
| Code Optimized for Xilinx? | No |
| Synthesis Software Tools Supported / version | Xilinx XST / 11.5, 12.1 |
| Static Timing Analysis Performed? | Yes |
| Standard IP Interface(s) Supported | None |
| IP-XACT Metadata Included? | No |
| Verfification | |
| Is a documented verification plan available? | Yes, document only plan |
| Test Methodology | Constrained-random testing |
| Assertions | Yes |
| Coverage Metrics Collected | Code; Functional |
| Timing Verification Performed? | Yes |
| Timing Verification Report Available | Yes |
| Simulators supported | Mentor ModelSIM / 6.5DE |
| Hardware Validation | |
| Validated on FPGA | Yes |
| Hardware validation platform used | Spartan-6 |
| Industry standard compliance testing passed | Yes |
| Specific compliance test | http://www.machinevisiononline.org |
| Test date | 2010-06-01 00:00:00.0 |
| Are test results available? | Yes |
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