Cadence® Incisive® Enterprise Simulator automates testbench generation, reuse, and analysis to verify designs from the system level, through RTL, to the gate level. Its metric-driven approach supports a coverage-driven methodology, from verification planning to closure. Its native-compiled architecture speeds the simultaneous simulation of behavioral, transaction-level, RTL, gate-level models, mixed-signal, and low-power eliminating the performance degradation often seen in other co-simulation approaches.
Key Features
- Compehesive core for digital and mixed-signal verification integrating all IEEE standard languages including SystemVerilog, e, SystemC, Verilog, VHDL, PSL, Verilog/VHDL-AMS, and Verilog/VHDL-A.
- Ensures verification quality by tracking industry-standard coverage metrics, including functional, transactional, and HDL code, plus automatic data and assertion checking.
- Delivers the highest possible performance for mixed-language designs, across multiple levels of abstraction, including the ability to “hot swap” the software simulation in/out of the Incisive Xtreme® series of accelerators/emulators.
- Provides unified debug across all digital and mixed-signal verification.
- Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs.
- Supports e, the Open Verification Library (OVL), the OVM class library, SystemC®, the SystemC Verification Library, SystemVerilog, Verilog®, VHDL, PSL, SVA, and the Si2 Common Power Format (CPF).
- Automates testbench generation, analysis, and reuse for increased productivity.
- Drives and guides verification with an automatically back annotated and executable verification plan.
Target Markets
- Wireless Communications
- Automotive
- Industrial Scientific Medical
- Broadcast
- High Performance Computing
- Consumer
- Wired Communications
- Aerospace & Defense