Memory Interface Generator (MIG)
AXI Interface Support:
- AXI4
Bundled With:
Both ISE and Vivado
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
- Vivado Design Suite
Product Details
Documentation
Device Family Support
- Artix-7
- Kintex-7 -2L
- Kintex-7
- Virtex-7
- Virtex-7 -2L
- Virtex-7 XT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Zynq-7000
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Spartan-6 LX
- Spartan-6 LXT
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Spartan-3E
- Spartan-3
Memory Interface Generator (MIG) is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs. MIG generates unencrypted Verilog or VHDL design files, UCF constraints, simulation files and implementation script files to simplify the design process. Memory Interfaces supported are: DDR3 SDRAM, DDR2 SDRAM, QDRII SRAM, and DDRII SRAM, LP DDR, QDRII+ SRAM, and RLDRAM II.
Key Features
- MIG generates through a Graphic User Interface the unencrypted Verilog or VHDL design files, UCF constraints, and simulation script files to simplify the memory interface design process.
- Memory modules (DIMM) are supported for DDR3, DDR2 and DDR SDRAMs.
- OS Support
- 64-bit/32-bit Linux Red hat Enterprise 4.0
- 64-bit XP Professional
- 32-bit Vista business
- 64-bit SUSE 10
- Windows XP