MorethanIP Programmable 1/2/4/8Gbps Fibre Channel Transport Core
Part Number:
MTIP-8000_FC_TR
Design Tools Support:
- ISE Design Suite
Device Family Support
- Virtex-6
- Virtex-5
The Fibre Channel (FC) is logically a bi-directional point-to-point serial data channel, structured for high performance information transport. Physically, Fibre Channel is an interconnection of one or more point-to-point links. Each link end terminates in a Port. Ports are fully specified in the Physical Interface (FC-PI) specification and Framing and Signaling (FC-FS) specification. Fibre is a general term used to cover all physical media supported by Fibre Channel including optical fiber, twisted pair, and coaxial cable. The 1/2/4/8 FC-2 Transport Core provides a generic solution for 1Gbps to 8Gbps Fibre Channel applications. The core is designed to support standard Fibre Channel applications such as point-to-point and fabric interconnect. On the Client side, the Core implements a 32-Bit FIFO interface running asynchronously from the Fibre Channel line clock. The FC-2 Layer provides services such as CRC generation / check, generate Fibre Compliant frames and maintains buffer-to-buffer credit and necessary Fibre Channel timers.The core is designed to support standard Fibre Channel applications such as point-to-point and fabric interconnect and can be used in conjunction with MorethanIP Ethernet Cores in FcoE (Fibre Channel over Ethernet) applications.
Key Features
- Configurable to support Gigabit , 2 Gigabit , 4 Gigabit or 8Gbps Fibre Channel applications.
- Implement Buffer-to-Buffer Credit management with credit recovery, credit reset and automatic R_RDY, BB_SCr and BB_SCs primitives generation.
- Implements Fibre Channel FC_PORT Port control state machine with programmable timers.
- Programmable maximum frame length to any value up to 4096 Bytes with default length set to 2136 bytes.
- CRC-32 checking at wire speed using a multi-stage CRC calculation architecture.
- Simple 32-Bit FIFO interface to user client application.
Target Markets
- Wired Communications
- Aerospace & Defense
- High Performance Computing
- Wireless Communications
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Virtex-5 | XC5VFX200T | ISE 11.1 | Yes | 6540 | 4357 | 13 | 0 | 4 | 1 | 212.5 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Nov 22,2010 |
| Company Name | MorethanIP GmbH |
| IP Name | MorethanIP Programmable 1/2/4/8Gbps Fibre Channel Transport Core |
| IP Part Number | MTIP-8000_FC_TR |
| Current IP Revision Number | 1.1 |
| Date Current Revision was Released | Dec 30,2008 |
| Release Date of first Version | Nov 30,2008 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 3 |
| Can references be made available? | No |
| Deliverables | |
| IP Formats available for purchase | Netlist; Source Code |
| Source Code Formats(s) | Verilog |
| Integration Techbench Format(s) | Verilog |
| Code Coverage Report Provided? | No |
| Functional Coverage Report Provided? | No |
| UCFs Provided? | Yes |
| Commercial Evaluation Board Available? | No |
| FPGA used on board | N/A |
| Software Drivers Provided? | N/A |
| Driver OS Support | N/A |
| Implementation | |
| Code Optimized for Xilinx? | No |
| Standard FPGA Optimization Techniques | Code Inference |
| Custom FPGA Optimization Techniques | Serdes and LVDS Macros instantiated on the top-level. |
| Synthesis Software Tools Supported / version | Xilinx XST / 11.1 |
| Static Timing Analysis Performed? | Yes |
| Standard IP Interface(s) Supported | None |
| IP-XACT Metadata Included? | No |
| Verfification | |
| Is a documented verification plan available? | Yes, executable and documented plan |
| Test Methodology | Directed testing |
| Assertions | No |
| Coverage Metrics Collected | None |
| Simulators supported | Mentor ModelSIM / 6.5a |
| Hardware Validation | |
| Validated on FPGA | Yes |
| Hardware validation platform used | Customer xc5vfx200t-2 board. |
| Industry standard compliance testing passed | Yes |
| Specific compliance test | N/A |
| Test date | 2009-11-30 00:00:00.0 |
| Are test results available? | No |
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