DVB-T/H Modulator
Part Number:
MVD_DVBTH
License:
SignOnce
Alliance Program Tier:
Certified
Design Tools Support:
- ISE Design Suite
- Vivado Design Suite
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 LXT
- Virtex-5
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Spartan-6 LX
- Spartan-6 LXT
- Spartan-3A
- Spartan-3E
- Spartan-3
The MVD DVB-T/H modulator is a drop-in module that includes the following functions : · Input data framer from DVB-SPI source (MPEG-TS flow) · DVB-T/H modulator (Energy dispersal, Reed Solomon encoder, Convolutional interleaver, FEC convolution encoder, Inner interleaver, QPSK/QAM symbol mapper, Framer with pilots & TPS inserter, IFFT and guard interval insertion) · Flexible Digital Upsampler · Modulator for IF output · Output for simple DAC (14 bits) or baseband outputs (2x16bits) · ETSI, DVB-T/H (EN 300 744 V1.5.1) Compliant · Drop-in module for Virtex-6™, Virtex-5™, Spartan-6™ and Spartan™-3/E/A FPGAs · Single clock (up to 140 MHz+ for Spartan-3/6™, 180 MHz+ for Virtex-5/6™) · Robust SPI input (discarding incorrect input packets) · PCR re-stamping · Single channel, supports hierarchical transmission · Configurable Convolutional Rate · Configurable in-depth interleaving for DVB-H · Programmable QPSK, 16-QAM and 64-QAM Symbol Mapping · Configurable support for 2k, 8k and 4k (DVB-H) OFDM modes · Programmable Guard Interval (1/4, 1/8, 1/16,1/32) · Supports variable channel width 5MHz to 8MHz · Intermediate frequency output for single DAC (14 bits) or baseband outputs (2 x 16 bits) · Single / multi channel · Fully synthesizable RTL VHDL design (not delivered) for easy customization · Design delivered as Netlist · MER > 42dB · Carrier Suppression > 45dB
Key Features
- Drop-in module for Virtex™-5, Virtex-4 and Spartan™-3 FPGAs.
- ETSI, DVB-T/H (EN 300 744 V1.5.1) Compliant baseband transmitter for Digital Terrestrial Television.
- MER > 41dB.
- PCR restamping.
- Programmable symbol mapping, OFDM mode, guard interval and convolutional rate - Supports variable channel width 5 MHz to 8 MHz.
- Robust SPI input (discarding of incorrect input packets).
- Single channel, supports hierarchical transmission.
Target Markets
- Broadcast
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2012.1 | Y | 2738 | 6272 | 39 | 31 | 1 | 0 | 150 |
| Spartan 6T Family | XC6SLX45T | -3 | ISE 13.4 | Y | 1888 | 6486 | 46 | 29 | 1 | 0 | 150 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Aug 07,2012 |
| Company Name | Multi Video Designs |
| IP Name | DVB-T/H Modulator |
| IP Part Number | MVD_DVBTH |
| Current IP Revision Number | 2.2 |
| Date Current Revision was Released | May 31,2012 |
| Release Date of first Version | Jan 31,2009 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 5 |
| Can references be made available? | Y |
| Deliverables | |
| IP Formats available for purchase | Bitstream; Netlist; Source Code |
| Source Code Formats(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Spartan-6 |
| Software Drivers Provided? | N/A |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Instantiation |
| Synthesis Software Tools Supported / version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators supported | Xilinx lSim |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | SP605/ML605/KC705 + Analog Devices AD9739 FMC Card |
| Industry standard compliance testing passed | N |
| Are test results available? | N |
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