Alliance Program Tier:
Device Family Support
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Spartan-6 LX
- Spartan-6 LXT
- Spartan-6 XA
- Spartan-3A DSP
- Spartan-3A XA
- Spartan-3A DSP XA
- Spartan-3E XA
- Spartan-3 XA
High Performance and Capacity Mixed HDL Simulation - ModelSim. Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim an excellent choice for Xilinx FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
- ModelSim PE: RTL and Gate-Level Simulation.
- ModelSim PE: Verilog, VHDL and SystemVerilog Design.
- ModelSim PE: Integrated Debug and Code Coverage.
- DE: VHDL, Verilog, PSL, and SystemVerilog design and assertions constructs.
- DE: Wave viewing and comparison; objects, watch, and memory windows increase debug productivity.
- DE: Standard support for Xilinx SecureIP.
- SE: Multi-language, high performance simulation engine.
- SE: Verilog, VHDL, SystemVerilog Design.
- SE: Integrated Debug and Code Coverage.
- High Performance Computing
- Industrial Scientific Medical
- Aerospace & Defense
- Wired Communications
- Wireless Communications
Products and/or services provided by Alliance Program Members are sold or licensed solely by the Member and not Xilinx. Please be advised that Xilinx hereby disclaims any warranties, express or implied, including warranties of merchantability, fitness for a particular purpose, or noninfringement with respect to any such products and/or services.