Mentor Graphics Questa verification platform

Device Family Support

• Virtex-6 HXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Spartan-6 LXT
• Spartan-6 XA
• Spartan-3A
• Spartan-3A DSP
• Spartan-3AN
• Spartan-3A XA
• Spartan-3A DSP XA
• Spartan-3E
• Spartan-3E XA
• Spartan-3 XA

The Questa® verification platform delivers the full value of advanced verification and debug technologies within a comprehensive verification solution based on a metrics-driven verification management system. Questa spans the levels of abstraction required for complex SoC and FPGA design and verification. Questa significantly increases the productivity and predictability of any verification methodology while improving design quality as well as visibility and control of the verification process.

Key Features

• High Performance and Capacity Mixed HDL Simulation: Questa combines high performance and capacity with comprehensive support of SystemVerilog, VHDL, and SystemC. Questa is the most comprehensive advanced verification platform reducing the risk of validating the most complex FPGA and SoC designs.
• Assertion Based Verification: Questa delivers a comprehensive, standards-based ABV solution, offering the choice of SystemVerilog, Property Specification Language (PSL), or both. To ease the adoption of ABV, Questa also includes the Questa Verification Library (QVL). QVL is a comprehensive SystemVerilog assertion checker and monitor library that makes it easier to adopt ABV. With built-in coverage measurements, QVL integrates into any coverage-based methodology. QVL assertions can be used with any simulator and is the only assertion library optimized for formal verification and emulation.
• Testbench Automation: Questa verification features enable the automatic creation of complex, input-stimulus combinations that are extremely time-consuming to create manually. Stimulus scenarios can be described in terms of constraints using SystemVerilog and SystemC Verification (SCV) library constructs. These constrained-random features help promote reuse at the testbench level, thereby reducing the number of testbenches that need to be written while increasing the amount of tests generated, bugs exposed, and verification coverage achieved.
• Questa Verification Management: The application of constrained-random test stimulus and metrics-driven verification dramatically increases the amount of data generated in the verification process. Questa Verification Management analyzes coverage and verification data, providing up-to-date information on the status of verification test suites and insight into how to improve the efficiency and effectiveness of the verification process. Questa Verification Management imports verification test plans and correlates coverage results to test plan objectives, delivering a powerful tool for managers and engineers to continuously track progress and efficiently deploy resources against plan, providing a level of process visibility and efficiency formerly unavailable.
• Integrated Multi-Language Debugging: The Questa debug environment fully supports all standard languages, and its GUI usage model is consistent across all languages and abstraction levels. Questa automatically recognizes key objects in the design and verification environment, providing intuitive ways to view and debug these objects. For example, finite state machines (FSM) are inferred, and an FSM debug window provides a natural way to visualize the current state and state transitions of the FSM over time. Verification environments that are constructed with the OVM class library are recognized as part of the overall simulation hierarchy, even though the components of the verification environment are dynamic class objects. Questa manages the hierarchy automatically. Questa helps automate the often time-consuming and tedious process of tracing causality from an observed error to the root cause of the bug. Through either a graphical or source based dataflow, the source and sink (driver and reader) relationships can be easily traversed to identify the origin of a bug.
• Low Power Verification: The management of power consumption is critical for many applications. The techniques required to manage power present unique design and verification challenges. Questa’s Power Aware Simulation (PASim), combined with Accellera’s Unified Power Format (UPF) standard, mitigates the risks of implementing low power silicon designs by accurately modeling low power silicon behavior early in the design cycle.

Target Markets

• Consumer
• Wireless Communications
• Automotive
• Aerospace & Defense
• High Performance Computing
• Wired Communications
• Broadcast
• Industrial Scientific Medical